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[Qemu-devel] [PATCH 4/4] pci/config: convert pci configuration space han
From: |
Isaku Yamahata |
Subject: |
[Qemu-devel] [PATCH 4/4] pci/config: convert pci configuration space handler to use callback. |
Date: |
Wed, 13 May 2009 16:50:52 +0900 |
convert pci configuration space handler into callbacks.
Signed-off-by: Isaku Yamahata <address@hidden>
---
hw/acpi.c | 11 ++++-----
hw/cirrus_vga.c | 11 +++++----
hw/gt64xxx.c | 13 +---------
hw/piix_pci.c | 18 +++++++++-----
hw/vga.c | 10 +++++---
hw/wdt_i6300esb.c | 66 +++++++++++++++++++++-------------------------------
6 files changed, 56 insertions(+), 73 deletions(-)
diff --git a/hw/acpi.c b/hw/acpi.c
index dbaf18a..ef11088 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -433,12 +433,10 @@ static void pm_io_space_update(PIIX4PMState *s)
}
}
-static void pm_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
+static void pm_write_config_0x80(struct PCIDevice *d,
+ uint32_t written, uint32_t mask)
{
- pci_default_write_config(d, address, val, len);
- if (address == 0x80)
- pm_io_space_update((PIIX4PMState *)d);
+ pm_io_space_update((PIIX4PMState *)d);
}
static void pm_save(QEMUFile* f,void *opaque)
@@ -505,7 +503,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
smb_io_base,
s = (PIIX4PMState *)pci_register_device(bus,
"PM", sizeof(PIIX4PMState),
- devfn, NULL, pm_write_config);
+ devfn, NULL, NULL);
+ pci_conf_initb(s->dev.config_regs, 0x80, pm_write_config_0x80, 1);
pm_state = s;
pci_conf = s->dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 8c5d1fc..5751636 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -3289,16 +3289,15 @@ static void cirrus_pci_mmio_map(PCIDevice *d, int
region_num,
s->cirrus_mmio_io_addr);
}
-static void pci_cirrus_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
+static void pci_cirrus_write_config_bar0(struct PCIDevice *d,
+ uint32_t written, uint32_t mask)
{
PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
CirrusVGAState *s = &pvs->cirrus_vga;
- pci_default_write_config(d, address, val, len);
+ pci_update_mappings(d);
if (s->vga.map_addr && pvs->dev.io_regions[0].addr == -1)
s->vga.map_addr = 0;
- cirrus_update_memory_access(s);
}
void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size)
@@ -3313,7 +3312,9 @@ void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size)
/* setup PCI configuration registers */
d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
sizeof(PCICirrusVGAState),
- -1, NULL,
pci_cirrus_write_config);
+ -1, NULL, NULL);
+ pci_conf_initl(d->dev.config_regs, PCI_BASE_ADDRESS_0,
+ pci_cirrus_write_config_bar0, 0);
pci_conf = d->dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
pci_config_set_device_id(pci_conf, device_id);
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 7fc91dd..2581cd0 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1083,17 +1083,6 @@ static void gt64120_reset(void *opaque)
gt64120_pci_mapping(s);
}
-static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
-{
- return pci_default_read_config(d, address, len);
-}
-
-static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
- int len)
-{
- pci_default_write_config(d, address, val, len);
-}
-
static void gt64120_save(QEMUFile* f, void *opaque)
{
PCIDevice *d = opaque;
@@ -1132,7 +1121,7 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
pic, 144, 4);
s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
- 0, gt64120_read_config, gt64120_write_config);
+ 0, NULL, NULL);
/* FIXME: Malta specific hw assumptions ahead */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 2b19cc6..d241882 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -128,13 +128,11 @@ void i440fx_init_memory_mappings(PCIDevice *d)
}
}
-static void i440fx_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
+/* XXX: implement SMRAM.D_LOCK */
+static void i440fx_write_config_0x59_0x5f_0x72(struct PCIDevice *d,
+ uint32_t written, uint32_t mask)
{
- /* XXX: implement SMRAM.D_LOCK */
- pci_default_write_config(d, address, val, len);
- if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
- i440fx_update_memory_mappings(d);
+ i440fx_update_memory_mappings(d);
}
static void i440fx_save(QEMUFile* f, void *opaque)
@@ -174,6 +172,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq
*pic)
PCIBus *b;
PCIDevice *d;
I440FXState *s;
+ uint32_t addr;
s = qemu_mallocz(sizeof(I440FXState));
b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
@@ -190,7 +189,12 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq
*pic)
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
- NULL, i440fx_write_config);
+ NULL, NULL);
+ for (addr = 0x59; addr <= 0x5f; addr++)
+ pci_conf_initb(d->config_regs, addr,
+ i440fx_write_config_0x59_0x5f_0x72, 0xff);
+ pci_conf_initb(d->config_regs, 0x72,
+ i440fx_write_config_0x59_0x5f_0x72, 0xff);
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
diff --git a/hw/vga.c b/hw/vga.c
index 2de92af..57e6044 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -2469,13 +2469,13 @@ int isa_vga_mm_init(int vga_ram_size,
target_phys_addr_t vram_base,
return 0;
}
-static void pci_vga_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
+static void pci_vga_write_config_bar0(struct PCIDevice *d,
+ uint32_t written, uint32_t mask)
{
PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
VGAState *s = &pvs->vga_state;
- pci_default_write_config(d, address, val, len);
+ pci_update_mappings(d);
if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
s->map_addr = 0;
}
@@ -2489,9 +2489,11 @@ int pci_vga_init(PCIBus *bus, int vga_ram_size,
d = (PCIVGAState *)pci_register_device(bus, "VGA",
sizeof(PCIVGAState),
- -1, NULL, pci_vga_write_config);
+ -1, NULL, NULL);
if (!d)
return -1;
+ pci_conf_initl(&d->dev.config_regs, PCI_BASE_ADDRESS_0,
+ pci_vga_write_config_bar0, 0);
s = &d->vga_state;
vga_common_init(s, vga_ram_size);
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index f7ddea2..9e90704 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -198,56 +198,39 @@ static void i6300esb_timer_expired(void *vp)
}
}
-static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
- uint32_t data, int len)
+static void i6300esb_config_write_esb_config_reg(struct PCIDevice *dev,
+ uint32_t data, uint32_t mask)
{
I6300State *d = (I6300State *) dev;
- int old;
i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
- if (addr == ESB_CONFIG_REG && len == 2) {
+ if (mask & ESB_WDT_REBOOT)
d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
+ if (mask & ESB_WDT_FREQ)
d->clock_scale =
(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
+ if (mask & ESB_WDT_INTTYPE)
d->int_type = (data & ESB_WDT_INTTYPE);
- } else if (addr == ESB_LOCK_REG && len == 1) {
- if (!d->locked) {
- d->locked = (data & ESB_WDT_LOCK) != 0;
- d->free_run = (data & ESB_WDT_FUNC) != 0;
- old = d->enabled;
- d->enabled = (data & ESB_WDT_ENABLE) != 0;
- if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
- i6300esb_restart_timer(d, 1);
- else if (!d->enabled)
- i6300esb_disable_timer(d);
- }
- } else {
- pci_default_write_config(dev, addr, data, len);
- }
}
-static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
+static void i6300esb_config_write_esb_lock_reg(struct PCIDevice *dev,
+ uint32_t data, uint32_t mask)
{
I6300State *d = (I6300State *) dev;
- uint32_t data;
-
- i6300esb_debug ("addr = %x, len = %d\n", addr, len);
-
- if (addr == ESB_CONFIG_REG && len == 2) {
- data =
- (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
- (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
- d->int_type;
- return data;
- } else if (addr == ESB_LOCK_REG && len == 1) {
- data =
- (d->free_run ? ESB_WDT_FUNC : 0) |
- (d->locked ? ESB_WDT_LOCK : 0) |
- (d->enabled ? ESB_WDT_ENABLE : 0);
- return data;
- } else {
- return pci_default_read_config(dev, addr, len);
+ int old;
+
+ i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
+
+ if (!d->locked) {
+ d->locked = (data & ESB_WDT_LOCK) != 0;
+ d->free_run = (data & ESB_WDT_FUNC) != 0;
+ old = d->enabled;
+ d->enabled = (data & ESB_WDT_ENABLE) != 0;
+ if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
+ i6300esb_restart_timer(d, 1);
+ else if (!d->enabled)
+ i6300esb_disable_timer(d);
}
}
@@ -429,8 +412,13 @@ static void i6300esb_pc_init(PCIBus *pci_bus)
d = (I6300State *)
pci_register_device (pci_bus, "i6300esb_wdt", sizeof (I6300State),
- -1,
- i6300esb_config_read, i6300esb_config_write);
+ -1, NULL, NULL);
+ pci_conf_initw(d->dev.config_regs, ESB_CONFIG_REG,
+ i6300esb_config_write_esb_config_reg,
+ ESB_WDT_REBOOT | ESB_WDT_FREQ | ESB_WDT_INTTYPE);
+ pci_conf_initb(d->dev.config_regs, ESB_LOCK_REG,
+ i6300esb_config_write_esb_lock_reg,
+ ESB_WDT_FUNC | ESB_WDT_LOCK | ESB_WDT_ENABLE);
d->reboot_enabled = 1;
d->clock_scale = CLOCK_SCALE_1KHZ;
--
1.6.0.2