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[Qemu-devel] [PATCH 17/24] Add instruction name in comments for hw_ld op
From: |
Tristan Gingold |
Subject: |
[Qemu-devel] [PATCH 17/24] Add instruction name in comments for hw_ld opcode. |
Date: |
Fri, 13 Mar 2009 15:20:36 +0100 |
Make code slightly easier to read.
Also unused hw_ld opcodes now generate an invalid opc fault.
Signed-off-by: Tristan Gingold <address@hidden>
---
target-alpha/translate.c | 40 ++++++++++++++++++++--------------------
1 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index df50d1c..51a628c 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1793,62 +1793,62 @@ static always_inline int translate_one (DisasContext
*ctx, uint32_t insn)
tcg_gen_movi_i64(addr, disp12);
switch ((insn >> 12) & 0xF) {
case 0x0:
- /* Longword physical access */
+ /* Longword physical access (hw_ldl/p) */
gen_helper_ldl_raw(cpu_ir[ra], addr);
break;
case 0x1:
- /* Quadword physical access */
+ /* Quadword physical access (hw_ldq/p) */
gen_helper_ldq_raw(cpu_ir[ra], addr);
break;
case 0x2:
- /* Longword physical access with lock */
+ /* Longword physical access with lock (hw_ldl_l/p) */
gen_helper_ldl_l_raw(cpu_ir[ra], addr);
break;
case 0x3:
- /* Quadword physical access with lock */
+ /* Quadword physical access with lock (hw_ldq_l/p) */
gen_helper_ldq_l_raw(cpu_ir[ra], addr);
break;
case 0x4:
- /* Longword virtual PTE fetch */
- gen_helper_ldl_kernel(cpu_ir[ra], addr);
+ /* Longword virtual PTE fetch (hw_ldl/v) */
+ tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
break;
case 0x5:
- /* Quadword virtual PTE fetch */
- gen_helper_ldq_kernel(cpu_ir[ra], addr);
+ /* Quadword virtual PTE fetch (hw_ldq/v) */
+ tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
break;
case 0x6:
/* Incpu_ir[ra]id */
- goto incpu_ir[ra]id_opc;
+ goto invalid_opc;
case 0x7:
/* Incpu_ir[ra]id */
- goto incpu_ir[ra]id_opc;
+ goto invalid_opc;
case 0x8:
- /* Longword virtual access */
+ /* Longword virtual access (hw_ldl) */
gen_helper_st_virt_to_phys(addr, addr);
gen_helper_ldl_raw(cpu_ir[ra], addr);
break;
case 0x9:
- /* Quadword virtual access */
+ /* Quadword virtual access (hw_ldq) */
gen_helper_st_virt_to_phys(addr, addr);
gen_helper_ldq_raw(cpu_ir[ra], addr);
break;
case 0xA:
- /* Longword virtual access with protection check */
- tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags);
+ /* Longword virtual access with protection check (hw_ldl/w) */
+ tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
break;
case 0xB:
- /* Quadword virtual access with protection check */
- tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags);
+ /* Quadword virtual access with protection check (hw_ldq/w) */
+ tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
break;
case 0xC:
- /* Longword virtual access with altenate access mode */
+ /* Longword virtual access with alt access mode (hw_ldl/a)*/
gen_helper_set_alt_mode();
gen_helper_st_virt_to_phys(addr, addr);
gen_helper_ldl_raw(cpu_ir[ra], addr);
gen_helper_restore_mode();
break;
case 0xD:
- /* Quadword virtual access with altenate access mode */
+ /* Quadword virtual access with alt access mode (hw_ldq/a) */
gen_helper_set_alt_mode();
gen_helper_st_virt_to_phys(addr, addr);
gen_helper_ldq_raw(cpu_ir[ra], addr);
@@ -1856,7 +1856,7 @@ static always_inline int translate_one (DisasContext
*ctx, uint32_t insn)
break;
case 0xE:
/* Longword virtual access with alternate access mode and
- * protection checks
+ * protection checks (hw_ldl/wa)
*/
gen_helper_set_alt_mode();
gen_helper_ldl_data(cpu_ir[ra], addr);
@@ -1864,7 +1864,7 @@ static always_inline int translate_one (DisasContext
*ctx, uint32_t insn)
break;
case 0xF:
/* Quadword virtual access with alternate access mode and
- * protection checks
+ * protection checks (hw_ldq/wa)
*/
gen_helper_set_alt_mode();
gen_helper_ldq_data(cpu_ir[ra], addr);
--
1.6.2
- [Qemu-devel] [PATCH 07/24] Increase Alpha physical address size to 44 bits., (continued)
- [Qemu-devel] [PATCH 07/24] Increase Alpha physical address size to 44 bits., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 08/24] Allow 5 mmu indexes., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 09/24] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 10/24] Add square wave output support., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 11/24] Add ali1543 super IO pci device., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 12/24] Add 21272 chipset (memory and pci controller for alpha), Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 13/24] Add target-alpha/machine.c with es40 machine emulation., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 14/24] Move softmmu_helper.h from exec.h to op_helper.c on alpha., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 15/24] Document which IPR are used by 21264., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 16/24] tb_flush helper should flush the tb (and not the tlb)., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 17/24] Add instruction name in comments for hw_ld opcode.,
Tristan Gingold <=
- [Qemu-devel] [PATCH 18/24] Remove PALCODE_ declarations (unused)., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 19/24] alpha ld helpers now directly return the value., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 20/24] Add alpha_cpu_list., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 21/24] Alpha: lower parent irq when irq is lowered., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 22/24] Move linux-user pal emulation to linux-user/, Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 23/24] Correctly decode hw_ld/hw_st opcodes for all alpha implementations., Tristan Gingold, 2009/03/13
- [Qemu-devel] [PATCH 24/24] Add full emulation for 21264., Tristan Gingold, 2009/03/13
- Re: [Qemu-devel] [PATCH 20/24] Add alpha_cpu_list., Blue Swirl, 2009/03/13
- Re: [Qemu-devel] [PATCH 20/24] Add alpha_cpu_list., Tristan Gingold, 2009/03/16
- Re: [Qemu-devel] [PATCH 13/24] Add target-alpha/machine.c with es40 machine emulation., Blue Swirl, 2009/03/13