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[Qemu-devel] [6608] qemu: pci hotplug GPE support (Marcelo Tosatti)
From: |
Anthony Liguori |
Subject: |
[Qemu-devel] [6608] qemu: pci hotplug GPE support (Marcelo Tosatti) |
Date: |
Wed, 11 Feb 2009 15:21:42 +0000 |
Revision: 6608
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6608
Author: aliguori
Date: 2009-02-11 15:21:41 +0000 (Wed, 11 Feb 2009)
Log Message:
-----------
qemu: pci hotplug GPE support (Marcelo Tosatti)
Enable the corresponding bit on the PCIST region and trigger the SCI
and handle the _EJ0 notifications.
Signed-off-by: Marcelo Tosatti <address@hidden>
Signed-off-by: Anthony Liguori <address@hidden>
Modified Paths:
--------------
trunk/hw/acpi.c
trunk/sysemu.h
Modified: trunk/hw/acpi.c
===================================================================
--- trunk/hw/acpi.c 2009-02-11 15:21:35 UTC (rev 6607)
+++ trunk/hw/acpi.c 2009-02-11 15:21:41 UTC (rev 6608)
@@ -563,13 +563,21 @@
#endif
#define GPE_BASE 0xafe0
+#define PCI_BASE 0xae00
+#define PCI_EJ_BASE 0xae08
struct gpe_regs {
uint16_t sts; /* status */
uint16_t en; /* enabled */
};
+struct pci_status {
+ uint32_t up;
+ uint32_t down;
+};
+
static struct gpe_regs gpe;
+static struct pci_status pci0_status;
static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
@@ -623,9 +631,95 @@
#endif
}
+static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ val = g->up;
+ break;
+ case PCI_BASE + 4:
+ val = g->down;
+ break;
+ default:
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("pcihotplug read %lx == %lx\n", addr, val);
+#endif
+ return val;
+}
+
+static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ g->up = val;
+ break;
+ case PCI_BASE + 4:
+ g->down = val;
+ break;
+ }
+
+#if defined(DEBUG)
+ printf("pcihotplug write %lx <== %d\n", addr, val);
+#endif
+}
+
+static uint32_t pciej_read(void *opaque, uint32_t addr)
+{
+#if defined(DEBUG)
+ printf("pciej read %lx == %lx\n", addr, val);
+#endif
+ return 0;
+}
+
+static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ int slot = ffs(val) - 1;
+
+#if defined(DEBUG)
+ printf("pciej write %lx <== %d\n", addr, val);
+#endif
+}
+
void qemu_system_hot_add_init(void)
{
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe);
+ register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
+ register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status);
+
+ register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
+ register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL);
}
+
+static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ g->en |= 2;
+ p->up |= (1 << slot);
+}
+
+static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ g->en |= 2;
+ p->down |= (1 << slot);
+}
+
+void qemu_system_device_hot_add(int bus, int slot, int state)
+{
+ qemu_set_irq(pm_state->irq, 1);
+ pci0_status.up = 0;
+ pci0_status.down = 0;
+ if (state)
+ enable_device(&pci0_status, &gpe, slot);
+ else
+ disable_device(&pci0_status, &gpe, slot);
+ qemu_set_irq(pm_state->irq, 0);
+}
Modified: trunk/sysemu.h
===================================================================
--- trunk/sysemu.h 2009-02-11 15:21:35 UTC (rev 6607)
+++ trunk/sysemu.h 2009-02-11 15:21:41 UTC (rev 6608)
@@ -168,6 +168,7 @@
/* acpi */
void qemu_system_hot_add_init(void);
+void qemu_system_device_hot_add(int pcibus, int slot, int state);
/* serial ports */
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