[Qemu-devel] [PATCH 23/42] target-ppc: add vsldoi instruction.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-ppc/helper.h    |    1 +
 target-ppc/op_helper.c |   28 ++++++++++++++++++++++++++++
 target-ppc/translate.c |   21 +++++++++++++++++++++
 3 files changed, 50 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5f94e9f..02e3c10 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -178,6 +178,7 @@ DEF_HELPER_3(vrlh, void, avr, avr, avr)
 DEF_HELPER_3(vrlw, void, avr, avr, avr)
 DEF_HELPER_3(vsl, void, avr, avr, avr)
 DEF_HELPER_3(vsr, void, avr, avr, avr)
+DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
 
 DEF_HELPER_1(efscfsi, i32, i32)
 DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 7d72767..310a46c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2313,6 +2313,34 @@ VSL(h, u16)
 VSL(w, u32)
 #undef VSL
 
+void helper_vsldoi (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
+{
+  int sh = shift & 0xf;
+  int i;
+  ppc_avr_t result;
+
+#if defined(WORDS_BIGENDIAN)
+  VECTOR_FOR_I (i, u8) {
+    int index = sh + i;
+    if (index > 0xf) {
+      result.u8[i] = b->u8[index-0x10];
+    } else {
+      result.u8[i] = a->u8[index];
+    }
+  }
+#else
+  VECTOR_FOR_I (i, u8) {
+    int index = (16 - sh) + i;
+    if (index > 0xf) {
+      result.u8[i] = a->u8[index-0x10];
+    } else {
+      result.u8[i] = b->u8[index];
+    }
+  }
+#endif
+  *r = result;
+}
+
 void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
   int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c072d54..33c9c40 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -378,6 +378,8 @@ EXTRACT_HELPER(UIMM, 0, 16);
 EXTRACT_HELPER(NB, 11, 5);
 /* Shift count */
 EXTRACT_HELPER(SH, 11, 5);
+/* Vector shift count */
+EXTRACT_HELPER(VSH, 6, 4);
 /* Mask start */
 EXTRACT_HELPER(MB, 6, 5);
 /* Mask end */
@@ -6330,6 +6332,25 @@ GEN_VXRFORM(vcmpgtub, 518)
 GEN_VXRFORM(vcmpgtuh, 582)
 GEN_VXRFORM(vcmpgtuw, 646)
 
+GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
+{
+    TCGv_ptr ra, rb, rd;
+    TCGv sh;
+    if (unlikely(!ctx->altivec_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VPU);
+        return;
+    }
+    ra = gen_avr_ptr(rA(ctx->opcode));
+    rb = gen_avr_ptr(rB(ctx->opcode));
+    rd = gen_avr_ptr(rD(ctx->opcode));
+    sh = tcg_const_i32(VSH(ctx->opcode));
+    gen_helper_vsldoi (rd, ra, rb, sh);
+    tcg_temp_free(ra);
+    tcg_temp_free(rb);
+    tcg_temp_free(rd);
+    tcg_temp_free(sh);
+}
+
 /***                           SPE extension                               ***/
 /* Register moves */
 
-- 
1.6.0.5