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Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG |
Date: |
Wed, 3 Sep 2008 01:20:51 +0200 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
On Wed, Sep 03, 2008 at 12:22:48AM +0200, Andreas Färber wrote:
> Replace op_load_gpr_T0, op_load_gpr_T1 and op_load_gpr_T2 with
> tcg_gen_mov_tl.
>
> To do so, introduce TCG variables cpu_gpr[0..31].
>
> Signed-off-by: Andreas Faerber <address@hidden>
> ---
> target-ppc/translate.c | 418 ++++++++++++++++++++++++++
> +---------------------
> 1 files changed, 233 insertions(+), 185 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 9068936..0fe119a 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -44,15 +44,57 @@
> /
> *****************************************************************************/
> /* Code translation helpers
> */
>
> -static TCGv cpu_env, cpu_T[3];
> +/* global register indexes */
> +static TCGv cpu_env;
> +static TCGv cpu_gpr[32];
> +
> +/* dyngen register indexes */
> +static TCGv cpu_T[3];
>
> #include "gen-icount.h"
>
> void ppc_translate_init(void)
> {
> + int i;
> static int done_init = 0;
> + static const char* const gprnames[32] = {
> + "r0",
> + "r1",
> + "r2",
> + "r3",
> + "r4",
> + "r5",
> + "r6",
> + "r7",
> + "r8",
> + "r9",
> + "r10",
> + "r11",
> + "r12",
> + "r13",
> + "r14",
> + "r15",
> + "r16",
> + "r17",
> + "r18",
> + "r19",
> + "r20",
> + "r21",
> + "r22",
> + "r23",
> + "r24",
> + "r25",
> + "r26",
> + "r27",
> + "r28",
> + "r29",
> + "r30",
> + "r31"
> + };
> +
You may want to use a sprintf() function instead (see other targets).
> if (done_init)
> return;
> +
> cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
> #if TARGET_LONG_BITS > HOST_LONG_BITS
> cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
> @@ -67,6 +109,12 @@ void ppc_translate_init(void)
> cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
> #endif
>
> + for (i = 0; i < 32; i++) {
> + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
> + offsetof(CPUState, gpr[i]),
> + gprnames[i]);
This is most probably wrong given the definition of ppc_gpr_t in cpu.h:
- 64 bits on 64-bit targets
- 32 bits on 32-bit targets and 32-bit hosts
- *64 bits* on 32-bit targets and 64-bit hosts
I think it is a bit weird, and I think the best is to modify cpu.h in
order to have ppc_gpr_t matching the target bitness.
Otherwise the patch looks ok. Care to also replace the ops in the same
patch? It's actually a general request, would nice to have a few more
instructions switched in a patch, to avoid spending to much time in
handling patches.
> + }
> +
> /* register helpers */
> #undef DEF_HELPER
> #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
> @@ -667,8 +715,8 @@ static opc_handler_t invalid_handler = {
> #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_gpr(rD(ctx->opcode));
> \
> if (unlikely(Rc(ctx->opcode) != 0))
> \
> @@ -678,8 +726,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_gpr(rD(ctx->opcode));
> \
> if (unlikely(Rc(ctx->opcode) != 0))
> \
> @@ -689,7 +737,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_gpr(rD(ctx->opcode));
> \
> if (unlikely(Rc(ctx->opcode) != 0))
> \
> @@ -698,7 +746,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800,
> type) \
> #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_gpr(rD(ctx->opcode));
> \
> if (unlikely(Rc(ctx->opcode) != 0))
> \
> @@ -723,8 +771,8 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10,
> type)
> #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> if (ctx->sf_mode)
> \
> gen_op_##name##_64();
> \
> else
> \
> @@ -737,8 +785,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> if (ctx->sf_mode)
> \
> gen_op_##name##_64();
> \
> else
> \
> @@ -751,7 +799,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)
> \
> #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> if (ctx->sf_mode)
> \
> gen_op_##name##_64();
> \
> else
> \
> @@ -763,7 +811,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800,
> type) \
> #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)
> \
> GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> if (ctx->sf_mode)
> \
> gen_op_##name##_64();
> \
> else
> \
> @@ -986,7 +1034,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* li case */
> tcg_gen_movi_tl(cpu_T[0], simm);
> } else {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> gen_op_addi(simm);
> }
> @@ -997,7 +1045,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> {
> target_long simm = SIMM(ctx->opcode);
>
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0)) {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> gen_op_addi(simm);
> @@ -1017,7 +1065,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF,
> 0x00000000, PPC_INTEGER)
> {
> target_long simm = SIMM(ctx->opcode);
>
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0)) {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> gen_op_addi(simm);
> @@ -1042,7 +1090,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* lis case */
> tcg_gen_movi_tl(cpu_T[0], simm << 16);
> } else {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> gen_op_addi(simm << 16);
> }
> @@ -1051,14 +1099,14 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* mulli */
> GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_mulli(SIMM(ctx->opcode));
> gen_op_store_T0_gpr(rD(ctx->opcode));
> }
> /* subfic */
> GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode)
> gen_op_subfic_64(SIMM(ctx->opcode));
> @@ -1086,8 +1134,8 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E,
> PPC_64B);
> #define GEN_CMP(name, opc, type)
> \
> GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> if (ctx->sf_mode && (ctx->opcode & 0x00200000))
> \
> gen_op_##name##_64();
> \
> else
> \
> @@ -1098,8 +1146,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000,
> type) \
> #define GEN_CMP(name, opc, type)
> \
> GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_crf(crfD(ctx->opcode));
> \
> }
> @@ -1110,7 +1158,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER);
> /* cmpi */
> GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode && (ctx->opcode & 0x00200000))
> gen_op_cmpi_64(SIMM(ctx->opcode));
> @@ -1124,7 +1172,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER);
> /* cmpli */
> GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode && (ctx->opcode & 0x00200000))
> gen_op_cmpli_64(UIMM(ctx->opcode));
> @@ -1143,9 +1191,9 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001,
> PPC_ISEL)
> if (rA(ctx->opcode) == 0) {
> tcg_gen_movi_tl(cpu_T[0], 0);
> } else {
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> }
> - gen_op_load_gpr_T2(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
> mask = 1 << (3 - (bi & 0x03));
> gen_op_load_crf_T0(bi >> 2);
> gen_op_test_true(mask);
> @@ -1157,8 +1205,8 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001,
> PPC_ISEL)
> #define __GEN_LOGICAL2(name, opc2, opc3, type)
> \
> GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> \
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_gpr(rA(ctx->opcode));
> \
> if (unlikely(Rc(ctx->opcode) != 0))
> \
> @@ -1170,7 +1218,7 @@ __GEN_LOGICAL2(name, 0x1C, opc, type)
> #define GEN_LOGICAL1(name, opc, type)
> \
> GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
> \
> {
> \
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> \
> gen_op_##name();
> \
> gen_op_store_T0_gpr(rA(ctx->opcode));
> \
> if (unlikely(Rc(ctx->opcode) != 0))
> \
> @@ -1184,7 +1232,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
> /* andi. */
> GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> gen_op_andi_T0(UIMM(ctx->opcode));
> gen_op_store_T0_gpr(rA(ctx->opcode));
> gen_set_Rc0(ctx);
> @@ -1192,7 +1240,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF,
> 0x00000000, PPC_INTEGER)
> /* andis. */
> GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> gen_op_andi_T0(UIMM(ctx->opcode) << 16);
> gen_op_store_T0_gpr(rA(ctx->opcode));
> gen_set_Rc0(ctx);
> @@ -1221,16 +1269,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000,
> PPC_INTEGER)
> rb = rB(ctx->opcode);
> /* Optimisation for mr. ri case */
> if (rs != ra || rs != rb) {
> - gen_op_load_gpr_T0(rs);
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
> if (rs != rb) {
> - gen_op_load_gpr_T1(rb);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
> gen_op_or();
> }
> gen_op_store_T0_gpr(ra);
> if (unlikely(Rc(ctx->opcode) != 0))
> gen_set_Rc0(ctx);
> } else if (unlikely(Rc(ctx->opcode) != 0)) {
> - gen_op_load_gpr_T0(rs);
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
> gen_set_Rc0(ctx);
> #if defined(TARGET_PPC64)
> } else {
> @@ -1286,10 +1334,10 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
> /* xor & xor. */
> GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> /* Optimisation for "set to zero" case */
> if (rS(ctx->opcode) != rB(ctx->opcode)) {
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_xor();
> } else {
> tcg_gen_movi_tl(cpu_T[0], 0);
> @@ -1308,7 +1356,7 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* XXX: should handle special NOPs for POWER series */
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (likely(uimm != 0))
> gen_op_ori(uimm);
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -1322,7 +1370,7 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* NOP */
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (likely(uimm != 0))
> gen_op_ori(uimm << 16);
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -1336,7 +1384,7 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* NOP */
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (likely(uimm != 0))
> gen_op_xori(uimm);
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -1351,7 +1399,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* NOP */
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (likely(uimm != 0))
> gen_op_xori(uimm << 16);
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -1360,7 +1408,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> /* popcntb : PowerPC 2.03 specification */
> GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode)
> gen_op_popcntb_64();
> @@ -1389,18 +1437,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF,
> 0x00000000, PPC_INTEGER)
> sh = SH(ctx->opcode);
> if (likely(sh == 0)) {
> if (likely(mb == 0 && me == 31)) {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> goto do_store;
> } else if (likely(mb == 31 && me == 0)) {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> goto do_store;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> goto do_mask;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> gen_op_rotli32_T0(SH(ctx->opcode));
> do_mask:
> #if defined(TARGET_PPC64)
> @@ -1424,7 +1472,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> sh = SH(ctx->opcode);
> mb = MB(ctx->opcode);
> me = ME(ctx->opcode);
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (likely(sh == 0)) {
> goto do_mask;
> }
> @@ -1461,8 +1509,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
>
> mb = MB(ctx->opcode);
> me = ME(ctx->opcode);
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_rotl32_T0_T1();
> if (unlikely(mb != 0 || me != 31)) {
> #if defined(TARGET_PPC64)
> @@ -1527,7 +1575,7 @@ static always_inline void gen_andi_T1_64
> (DisasContext *ctx, uint64_t mask)
> static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
> uint32_t me, uint32_t sh)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (likely(sh == 0)) {
> goto do_mask;
> }
> @@ -1587,8 +1635,8 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04);
> static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
> uint32_t me)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_rotl64_T0_T1();
> if (unlikely(mb != 0 || me != 63)) {
> gen_andi_T0_64(ctx, MASK(mb, me));
> @@ -1627,15 +1675,15 @@ static always_inline void gen_rldimi
> (DisasContext *ctx, int mbn, int shn)
> me = 63 - sh;
> if (likely(sh == 0)) {
> if (likely(mb == 0)) {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> goto do_store;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> goto do_mask;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> gen_op_rotli64_T0(sh);
> do_mask:
> mask = MASK(mb, me);
> @@ -1659,7 +1707,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
> GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
> {
> int mb, me;
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (SH(ctx->opcode) != 0) {
> tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
> mb = 32 - SH(ctx->opcode);
> @@ -1688,7 +1736,7 @@ static always_inline void gen_sradi (DisasContext
> *ctx, int n)
> uint64_t mask;
> int sh, mb, me;
>
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> sh = SH(ctx->opcode) + (n << 5);
> if (sh != 0) {
> tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
> @@ -2082,7 +2130,7 @@ static always_inline void gen_addr_imm_index
> (DisasContext *ctx,
> if (rA(ctx->opcode) == 0) {
> tcg_gen_movi_tl(cpu_T[0], simm);
> } else {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> gen_op_addi(simm);
> }
> @@ -2094,10 +2142,10 @@ static always_inline void gen_addr_imm_index
> (DisasContext *ctx,
> static always_inline void gen_addr_reg_index (DisasContext *ctx)
> {
> if (rA(ctx->opcode) == 0) {
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> } else {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_add();
> }
> #ifdef DEBUG_MEMORY_ACCESSES
> @@ -2110,7 +2158,7 @@ static always_inline void gen_addr_register
> (DisasContext *ctx)
> if (rA(ctx->opcode) == 0) {
> tcg_gen_movi_tl(cpu_T[0], 0);
> } else {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> }
> #ifdef DEBUG_MEMORY_ACCESSES
> gen_op_print_mem_EA();
> @@ -2309,7 +2357,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000,
> PPC_64BX)
> GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)
> \
> {
> \
> gen_addr_imm_index(ctx, 0);
> \
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> \
> op_ldst(st##width);
> \
> }
>
> @@ -2324,7 +2372,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF,
> 0x00000000, type) \
> gen_addr_imm_index(ctx, 0x03);
> \
> else
> \
> gen_addr_imm_index(ctx, 0);
> \
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> \
> op_ldst(st##width);
> \
> gen_op_store_T0_gpr(rA(ctx->opcode));
> \
> }
> @@ -2337,7 +2385,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3,
> 0x00000001, type) \
> return;
> \
> }
> \
> gen_addr_reg_index(ctx);
> \
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> \
> op_ldst(st##width);
> \
> gen_op_store_T0_gpr(rA(ctx->opcode));
> \
> }
> @@ -2346,7 +2394,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3,
> 0x00000001, type) \
> GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)
> \
> {
> \
> gen_addr_reg_index(ctx);
> \
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> \
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> \
> op_ldst(st##width);
> \
> }
>
> @@ -2391,10 +2439,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000,
> PPC_64B)
> return;
> }
> gen_addr_imm_index(ctx, 0x03);
> - gen_op_load_gpr_T1(rs);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
> op_ldst(std);
> gen_op_addi(8);
> - gen_op_load_gpr_T1(rs + 1);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
> op_ldst(std);
> #endif
> } else {
> @@ -2406,7 +2454,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000,
> PPC_64B)
> }
> }
> gen_addr_imm_index(ctx, 0x03);
> - gen_op_load_gpr_T1(rs);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
> op_ldst(std);
> if (Rc(ctx->opcode))
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -2599,7 +2647,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04,
> 0x00000000, PPC_RES)
> /* NIP cannot be restored if the memory exception comes from an
> helper */
> gen_update_nip(ctx, ctx->nip - 4);
> gen_addr_reg_index(ctx);
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> op_stwcx();
> }
>
> @@ -2629,7 +2677,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06,
> 0x00000000, PPC_64B)
> /* NIP cannot be restored if the memory exception comes from an
> helper */
> gen_update_nip(ctx, ctx->nip - 4);
> gen_addr_reg_index(ctx);
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> op_stdcx();
> }
> #endif /* defined(TARGET_PPC64) */
> @@ -3154,8 +3202,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D,
> PPC_FLOW)
> /* tw */
> GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> /* Update the nip since this might generate a trap exception */
> gen_update_nip(ctx, ctx->nip);
> gen_op_tw(TO(ctx->opcode));
> @@ -3164,7 +3212,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001,
> PPC_FLOW)
> /* twi */
> GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
> /* Update the nip since this might generate a trap exception */
> gen_update_nip(ctx, ctx->nip);
> @@ -3175,8 +3223,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000,
> PPC_FLOW)
> /* td */
> GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> /* Update the nip since this might generate a trap exception */
> gen_update_nip(ctx, ctx->nip);
> gen_op_td(TO(ctx->opcode));
> @@ -3185,7 +3233,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001,
> PPC_64B)
> /* tdi */
> GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
> /* Update the nip since this might generate a trap exception */
> gen_update_nip(ctx, ctx->nip);
> @@ -3309,7 +3357,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801,
> PPC_MISC)
> {
> uint32_t crm, crn;
>
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> crm = CRM(ctx->opcode);
> if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
> crn = ffs(crm);
> @@ -3332,7 +3380,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801,
> PPC_64B)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (ctx->opcode & 0x00010000) {
> /* Special form that does not need any synchronisation */
> gen_op_update_riee();
> @@ -3360,7 +3408,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801,
> PPC_MISC)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> if (ctx->opcode & 0x00010000) {
> /* Special form that does not need any synchronisation */
> gen_op_update_riee();
> @@ -3399,7 +3447,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001,
> PPC_MISC)
> write_cb = ctx->spr_cb[sprn].uea_write;
> if (likely(write_cb != NULL)) {
> if (likely(write_cb != SPR_NOACCESS)) {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> (*write_cb)(ctx, sprn);
> } else {
> /* Privilege exception */
> @@ -3628,7 +3676,7 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001,
> PPC_SEGMENT)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_srli_T1(28);
> gen_op_load_sr();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> @@ -3645,7 +3693,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801,
> PPC_SEGMENT)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
> gen_op_store_sr();
> #endif
> @@ -3661,8 +3709,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001,
> PPC_SEGMENT)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_srli_T1(28);
> gen_op_store_sr();
> #endif
> @@ -3697,7 +3745,7 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13,
> 0x14, 0x001F0001,
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_srli_T1(28);
> gen_op_load_slb();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> @@ -3714,7 +3762,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06,
> 0x0010F801, PPC_SEGMENT_64B)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
> gen_op_store_slb();
> #endif
> @@ -3731,8 +3779,8 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12,
> 0x07, 0x001F0001,
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_srli_T1(28);
> gen_op_store_slb();
> #endif
> @@ -3765,7 +3813,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001,
> PPC_MEM_TLBIE)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode)
> gen_op_tlbie_64();
> @@ -3817,7 +3865,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001,
> PPC_SLBI)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> gen_op_slbie();
> #endif
> }
> @@ -3848,7 +3896,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001,
> PPC_EXTERN)
> {
> /* Should check EAR[E] & alignment ! */
> gen_addr_reg_index(ctx);
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> op_ecowx();
> }
>
> @@ -3856,7 +3904,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001,
> PPC_EXTERN)
> /* abs - abs. */
> GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_POWER_abs();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3866,7 +3914,7 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800,
> PPC_POWER_BR)
> /* abso - abso. */
> GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_POWER_abso();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3876,7 +3924,7 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800,
> PPC_POWER_BR)
> /* clcs */
> GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_POWER_clcs();
> /* Rc=1 sets CR0 to an undefined state */
> gen_op_store_T0_gpr(rD(ctx->opcode));
> @@ -3885,8 +3933,8 @@ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800,
> PPC_POWER_BR)
> /* div - div. */
> GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_div();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3896,8 +3944,8 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000,
> PPC_POWER_BR)
> /* divo - divo. */
> GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_divo();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3907,8 +3955,8 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000,
> PPC_POWER_BR)
> /* divs - divs. */
> GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_divs();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3918,8 +3966,8 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000,
> PPC_POWER_BR)
> /* divso - divso. */
> GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_divso();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3929,8 +3977,8 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000,
> PPC_POWER_BR)
> /* doz - doz. */
> GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_doz();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3940,8 +3988,8 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000,
> PPC_POWER_BR)
> /* dozo - dozo. */
> GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_dozo();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -3951,7 +3999,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000,
> PPC_POWER_BR)
> /* dozi */
> GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
> gen_op_POWER_doz();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> @@ -4001,8 +4049,8 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000,
> PPC_POWER_BR)
> /* maskg - maskg. */
> GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_maskg();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4012,9 +4060,9 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000,
> PPC_POWER_BR)
> /* maskir - maskir. */
> GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> - gen_op_load_gpr_T2(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_maskir();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4024,8 +4072,8 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000,
> PPC_POWER_BR)
> /* mul - mul. */
> GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_mul();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4035,8 +4083,8 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000,
> PPC_POWER_BR)
> /* mulo - mulo. */
> GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_mulo();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4046,7 +4094,7 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000,
> PPC_POWER_BR)
> /* nabs - nabs. */
> GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_POWER_nabs();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4056,7 +4104,7 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000,
> PPC_POWER_BR)
> /* nabso - nabso. */
> GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_POWER_nabso();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4070,9 +4118,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000,
> PPC_POWER_BR)
>
> mb = MB(ctx->opcode);
> me = ME(ctx->opcode);
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> - gen_op_load_gpr_T2(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4082,9 +4130,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000,
> PPC_POWER_BR)
> /* rrib - rrib. */
> GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rA(ctx->opcode));
> - gen_op_load_gpr_T2(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_rrib();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4094,8 +4142,8 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000,
> PPC_POWER_BR)
> /* sle - sle. */
> GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_sle();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4105,8 +4153,8 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000,
> PPC_POWER_BR)
> /* sleq - sleq. */
> GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_sleq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4116,7 +4164,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000,
> PPC_POWER_BR)
> /* sliq - sliq. */
> GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
> gen_op_POWER_sle();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -4127,7 +4175,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000,
> PPC_POWER_BR)
> /* slliq - slliq. */
> GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
> gen_op_POWER_sleq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -4138,8 +4186,8 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000,
> PPC_POWER_BR)
> /* sllq - sllq. */
> GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_sllq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4149,8 +4197,8 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000,
> PPC_POWER_BR)
> /* slq - slq. */
> GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_slq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4160,7 +4208,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000,
> PPC_POWER_BR)
> /* sraiq - sraiq. */
> GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
> gen_op_POWER_sraq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -4171,8 +4219,8 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000,
> PPC_POWER_BR)
> /* sraq - sraq. */
> GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_sraq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4182,8 +4230,8 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000,
> PPC_POWER_BR)
> /* sre - sre. */
> GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_sre();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4193,8 +4241,8 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000,
> PPC_POWER_BR)
> /* srea - srea. */
> GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_srea();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4204,8 +4252,8 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000,
> PPC_POWER_BR)
> /* sreq */
> GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_sreq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4215,7 +4263,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000,
> PPC_POWER_BR)
> /* sriq */
> GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
> gen_op_POWER_srq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -4226,8 +4274,8 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000,
> PPC_POWER_BR)
> /* srliq */
> GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
> gen_op_POWER_srlq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> @@ -4238,8 +4286,8 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000,
> PPC_POWER_BR)
> /* srlq */
> GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_srlq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4249,8 +4297,8 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000,
> PPC_POWER_BR)
> /* srq */
> GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_POWER_srq();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -4282,7 +4330,7 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801,
> PPC_602_SPEC)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_602_mfrom();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> #endif
> @@ -4299,7 +4347,7 @@ GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E,
> 0x03FF0001, PPC_6xx_TLB)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> gen_op_6xx_tlbld();
> #endif
> }
> @@ -4314,7 +4362,7 @@ GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F,
> 0x03FF0001, PPC_6xx_TLB)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> gen_op_6xx_tlbli();
> #endif
> }
> @@ -4330,7 +4378,7 @@ GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12,
> 0x1E, 0x03FF0001, PPC_74xx_TLB)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> gen_op_74xx_tlbld();
> #endif
> }
> @@ -4345,7 +4393,7 @@ GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12,
> 0x1F, 0x03FF0001, PPC_74xx_TLB)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
> gen_op_74xx_tlbli();
> #endif
> }
> @@ -4594,8 +4642,8 @@ static always_inline void gen_405_mulladd_insn
> (DisasContext *ctx,
> int opc2, int opc3,
> int ra, int rb, int rt,
> int Rc)
> {
> - gen_op_load_gpr_T0(ra);
> - gen_op_load_gpr_T1(rb);
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
> switch (opc3 & 0x0D) {
> case 0x05:
> /* macchw - macchw. - macchwo - macchwo. */
> @@ -4646,7 +4694,7 @@ static always_inline void gen_405_mulladd_insn
> (DisasContext *ctx,
> }
> if (opc2 & 0x04) {
> /* (n)multiply-and-accumulate (0x0C - 0x0E) */
> - gen_op_load_gpr_T2(rt);
> + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
> tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
> gen_op_405_add_T0_T2();
> }
> @@ -4795,7 +4843,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001,
> PPC_DCR)
> return;
> }
> tcg_gen_movi_tl(cpu_T[0], dcrn);
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> gen_op_store_dcr();
> #endif
> }
> @@ -4811,7 +4859,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000,
> PPC_DCRX)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_load_dcr();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> /* Note: Rc update flag set leads to undefined state of Rc0 */
> @@ -4829,8 +4877,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000,
> PPC_DCRX)
> GEN_EXCP_PRIVREG(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> gen_op_store_dcr();
> /* Note: Rc update flag set leads to undefined state of Rc0 */
> #endif
> @@ -4839,7 +4887,7 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000,
> PPC_DCRX)
> /* mfdcrux (PPC 460) : user-mode access to DCR */
> GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_load_dcr();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> /* Note: Rc update flag set leads to undefined state of Rc0 */
> @@ -4848,8 +4896,8 @@ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000,
> PPC_DCRUX)
> /* mtdcrux (PPC 460) : user-mode access to DCR */
> GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
> {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> gen_op_store_dcr();
> /* Note: Rc update flag set leads to undefined state of Rc0 */
> }
> @@ -4998,12 +5046,12 @@ GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12,
> 0x1D, 0x00000001, PPC_40x_TLB)
> }
> switch (rB(ctx->opcode)) {
> case 0:
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_4xx_tlbre_hi();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> break;
> case 1:
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_4xx_tlbre_lo();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> break;
> @@ -5044,13 +5092,13 @@ GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12,
> 0x1E, 0x00000001, PPC_40x_TLB)
> }
> switch (rB(ctx->opcode)) {
> case 0:
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> gen_op_4xx_tlbwe_hi();
> break;
> case 1:
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> gen_op_4xx_tlbwe_lo();
> break;
> default:
> @@ -5075,7 +5123,7 @@ GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D,
> 0x00000001, PPC_BOOKE)
> case 0:
> case 1:
> case 2:
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> gen_op_440_tlbre(rB(ctx->opcode));
> gen_op_store_T0_gpr(rD(ctx->opcode));
> break;
> @@ -5118,8 +5166,8 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E,
> 0x00000001, PPC_BOOKE)
> case 0:
> case 1:
> case 2:
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rS(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
> gen_op_440_tlbwe(rB(ctx->opcode));
> break;
> default:
> @@ -5139,7 +5187,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01,
> PPC_WRTEE)
> GEN_EXCP_PRIVOPC(ctx);
> return;
> }
> - gen_op_load_gpr_T0(rD(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
> gen_op_wrte();
> /* Stop translation to have a chance to raise an exception
> * if we just set msr_ee to 1
> @@ -5171,8 +5219,8 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01,
> PPC_WRTEE)
> /* dlmzb */
> GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
> {
> - gen_op_load_gpr_T0(rS(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_440_dlmzb();
> gen_op_store_T0_gpr(rA(ctx->opcode));
> gen_op_store_xer_bc();
> @@ -5317,7 +5365,7 @@ static always_inline void gen_addr_spe_imm_index
> (DisasContext *ctx, int sh)
> if (rA(ctx->opcode) == 0) {
> tcg_gen_movi_tl(cpu_T[0], simm << sh);
> } else {
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> gen_op_addi(simm << sh);
> }
> @@ -5465,8 +5513,8 @@ GEN_SPEOP_ARITH1(evcntlsw);
> static always_inline void gen_brinc (DisasContext *ctx)
> {
> /* Note: brinc is usable even if SPE is disabled */
> - gen_op_load_gpr_T0(rA(ctx->opcode));
> - gen_op_load_gpr_T1(rB(ctx->opcode));
> + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_brinc();
> gen_op_store_T0_gpr(rD(ctx->opcode));
> }
> --
> 1.5.5.1
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' address@hidden | address@hidden
`- people.debian.org/~aurel32 | www.aurel32.net
- [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG, Andreas Färber, 2008/09/02
- [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG, Andreas Färber, 2008/09/02
- [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 to TCG, Andreas Färber, 2008/09/02
- Re: [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 to TCG, Aurelien Jarno, 2008/09/02
- [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 to TCG, Andreas Färber, 2008/09/02
- [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG, Andreas Färber, 2008/09/02
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG,
Aurelien Jarno <=
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/02
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Aurelien Jarno, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Thiemo Seufer, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Blue Swirl, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Blue Swirl, 2008/09/03
- [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves to TCG, Aurelien Jarno, 2008/09/04