[Qemu-devel] [5119] SH4: Convert shift functions to TCG

[Aurelien Jarno]

Revision: 5119
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5119
Author:   aurel32
Date:     2008-08-30 22:37:17 +0000 (Sat, 30 Aug 2008)

Log Message:
-----------
SH4: Convert shift functions to TCG

Signed-off-by: Aurelien Jarno <address@hidden>

Modified Paths:
--------------
    trunk/target-sh4/op.c
    trunk/target-sh4/translate.c

Modified: trunk/target-sh4/op.c
===================================================================
--- trunk/target-sh4/op.c       2008-08-30 22:07:52 UTC (rev 5118)
+++ trunk/target-sh4/op.c       2008-08-30 22:37:17 UTC (rev 5119)
@@ -115,27 +115,6 @@
     RETURN();
 }
 
-void OPPROTO op_shal_Rn(void)
-{
-    cond_t(env->gregs[PARAM1] & 0x80000000);
-    env->gregs[PARAM1] <<= 1;
-    RETURN();
-}
-
-void OPPROTO op_shar_Rn(void)
-{
-    cond_t(env->gregs[PARAM1] & 1);
-    *(int32_t *)&env->gregs[PARAM1] >>= 1;
-    RETURN();
-}
-
-void OPPROTO op_shlr_Rn(void)
-{
-    cond_t(env->gregs[PARAM1] & 1);
-    env->gregs[PARAM1] >>= 1;
-    RETURN();
-}
-
 void OPPROTO op_fmov_frN_FT0(void)
 {
     FT0 = env->fregs[PARAM1];

Modified: trunk/target-sh4/translate.c
===================================================================
--- trunk/target-sh4/translate.c        2008-08-30 22:07:52 UTC (rev 5118)
+++ trunk/target-sh4/translate.c        2008-08-30 22:37:17 UTC (rev 5119)
@@ -1226,13 +1226,19 @@
        return;
     case 0x4000:               /* shll Rn */
     case 0x4020:               /* shal Rn */
-       gen_op_shal_Rn(REG(B11_8));
+       tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000);
+       gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0);
+       tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
        return;
     case 0x4021:               /* shar Rn */
-       gen_op_shar_Rn(REG(B11_8));
+       tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1);
+       gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0);
+       tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
        return;
     case 0x4001:               /* shlr Rn */
-       gen_op_shlr_Rn(REG(B11_8));
+       tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1);
+       gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0);
+       tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1);
        return;
     case 0x4008:               /* shll2 Rn */
        tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);