[Qemu-devel] [4881] Fix MMU registers, add more E-cache ASIs

[Blue Swirl]

Revision: 4881
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4881
Author:   blueswir1
Date:     2008-07-16 16:58:49 +0000 (Wed, 16 Jul 2008)

Log Message:
-----------
Fix MMU registers, add more E-cache ASIs

Modified Paths:
--------------
    trunk/target-sparc/op_helper.c

Modified: trunk/target-sparc/op_helper.c
===================================================================
--- trunk/target-sparc/op_helper.c      2008-07-16 16:55:52 UTC (rev 4880)
+++ trunk/target-sparc/op_helper.c      2008-07-16 16:58:49 UTC (rev 4881)
@@ -1649,19 +1649,43 @@
         }
     case 0x51: // I-MMU 8k TSB pointer
     case 0x52: // I-MMU 64k TSB pointer
-    case 0x55: // I-MMU data access
         // XXX
         break;
+    case 0x55: // I-MMU data access
+        {
+            int reg = (addr >> 3) & 0x3f;
+
+            ret = env->itlb_tte[reg];
+            break;
+        }
     case 0x56: // I-MMU tag read
         {
             unsigned int i;
 
             for (i = 0; i < 64; i++) {
                 // Valid, ctx match, vaddr match
-                if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
-                    env->itlb_tag[i] == addr) {
-                    ret = env->itlb_tag[i];
-                    break;
+                if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
+                    uint64_t mask;
+
+                    switch ((env->itlb_tte[i] >> 61) & 3) {
+                    default:
+                    case 0x0:
+                        mask = 0xffffffffffffffff;
+                        break;
+                    case 0x1:
+                        mask = 0xffffffffffff0fff;
+                        break;
+                    case 0x2:
+                        mask = 0xfffffffffff80fff;
+                        break;
+                    case 0x3:
+                        mask = 0xffffffffffc00fff;
+                        break;
+                    }
+                    if ((env->itlb_tag[i] & mask) == (addr & mask)) {
+                        ret = env->itlb_tte[i];
+                        break;
+                    }
                 }
             }
             break;
@@ -1673,22 +1697,50 @@
             ret = env->dmmuregs[reg];
             break;
         }
+    case 0x5d: // D-MMU data access
+        {
+            int reg = (addr >> 3) & 0x3f;
+
+            ret = env->dtlb_tte[reg];
+            break;
+        }
     case 0x5e: // D-MMU tag read
         {
             unsigned int i;
 
             for (i = 0; i < 64; i++) {
                 // Valid, ctx match, vaddr match
-                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
-                    env->dtlb_tag[i] == addr) {
-                    ret = env->dtlb_tag[i];
-                    break;
+                if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
+                    uint64_t mask;
+
+                    switch ((env->dtlb_tte[i] >> 61) & 3) {
+                    default:
+                    case 0x0:
+                        mask = 0xffffffffffffffff;
+                        break;
+                    case 0x1:
+                        mask = 0xffffffffffff0fff;
+                        break;
+                    case 0x2:
+                        mask = 0xfffffffffff80fff;
+                        break;
+                    case 0x3:
+                        mask = 0xffffffffffc00fff;
+                        break;
+                    }
+                    if ((env->dtlb_tag[i] & mask) == (addr & mask)) {
+                        ret = env->dtlb_tte[i];
+                        break;
+                    }
                 }
             }
             break;
         }
     case 0x46: // D-cache data
     case 0x47: // D-cache tag access
+    case 0x4b: // E-cache error enable
+    case 0x4c: // E-cache asynchronous fault status
+    case 0x4d: // E-cache asynchronous fault address
     case 0x4e: // E-cache tag data
     case 0x66: // I-cache instruction access
     case 0x67: // I-cache tag access
@@ -1700,7 +1752,6 @@
     case 0x59: // D-MMU 8k TSB pointer
     case 0x5a: // D-MMU 64k TSB pointer
     case 0x5b: // D-MMU data pointer
-    case 0x5d: // D-MMU data access
     case 0x48: // Interrupt dispatch, RO
     case 0x49: // Interrupt data receive
     case 0x7f: // Incoming interrupt vector, RO
@@ -2052,6 +2103,9 @@
         return;
     case 0x46: // D-cache data
     case 0x47: // D-cache tag access
+    case 0x4b: // E-cache error enable
+    case 0x4c: // E-cache asynchronous fault status
+    case 0x4d: // E-cache asynchronous fault address
     case 0x4e: // E-cache tag data
     case 0x66: // I-cache instruction access
     case 0x67: // I-cache tag access