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[Qemu-devel] [PATCH 2/15] Introduce SSTEP_INTERNAL
From: |
Jan Kiszka |
Subject: |
[Qemu-devel] [PATCH 2/15] Introduce SSTEP_INTERNAL |
Date: |
Mon, 23 Jun 2008 16:24:10 +0200 |
User-agent: |
Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 |
Introducing SSTEP_INTERNAL, this patch allows to reuse the (host-
injected) single-step infrastructure to let the emulator generate and
execute TBs that only include a single instruction.
Signed-off-by: Jan Kiszka <address@hidden>
---
cpu-all.h | 7 ++++---
cpu-exec.c | 4 +++-
exec.c | 2 ++
gdbstub.c | 4 ++--
target-arm/translate.c | 2 +-
target-cris/translate.c | 2 +-
target-i386/translate.c | 2 +-
target-m68k/translate.c | 4 ++--
target-mips/translate.c | 2 +-
target-ppc/translate.c | 2 +-
target-sh4/translate.c | 6 +++---
vl.c | 7 ++++---
12 files changed, 25 insertions(+), 19 deletions(-)
Index: b/cpu-all.h
===================================================================
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -804,9 +804,10 @@ int cpu_breakpoint_insert(CPUState *env,
int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
void cpu_breakpoint_remove_all(CPUState *env);
-#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
-#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
-#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
+#define SSTEP_DEBUG 0x1 /* Enable simulated HW single stepping */
+#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
+#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
+#define SSTEP_INTERNAL 0x8 /* QEMU internal, do not generate breakpoint */
void cpu_single_step(CPUState *env, int enabled);
void cpu_reset(CPUState *s);
Index: b/cpu-exec.c
===================================================================
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -358,7 +358,8 @@ int cpu_exec(CPUState *env1)
for(;;) {
interrupt_request = env->interrupt_request;
if (unlikely(interrupt_request) &&
- likely(!(env->singlestep_enabled & SSTEP_NOIRQ))) {
+ likely(!(env->singlestep_enabled &
+ (SSTEP_NOIRQ | SSTEP_INTERNAL)))) {
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
env->exception_index = EXCP_DEBUG;
@@ -614,6 +615,7 @@ int cpu_exec(CPUState *env1)
#endif
next_tb = tcg_qemu_tb_exec(tc_ptr);
env->current_tb = NULL;
+ env->singlestep_enabled &= ~SSTEP_INTERNAL;
/* reset soft MMU for next block (it can currently
only be set by a memory fault) */
#if defined(USE_KQEMU)
Index: b/exec.c
===================================================================
--- a/exec.c
+++ b/exec.c
@@ -1316,6 +1316,8 @@ int cpu_breakpoint_remove(CPUState *env,
void cpu_single_step(CPUState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
+ enabled &= SSTEP_DEBUG | SSTEP_NOIRQ | SSTEP_NOTIMER;
+ enabled |= env->singlestep_enabled & SSTEP_INTERNAL;
if (env->singlestep_enabled != enabled) {
env->singlestep_enabled = enabled;
/* must flush all the translated code to avoid inconsistancies */
Index: b/target-arm/translate.c
===================================================================
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8666,7 +8666,7 @@ static inline int gen_intermediate_code_
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(env->singlestep_enabled & SSTEP_DEBUG)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
gen_set_condexec(dc);
Index: b/target-cris/translate.c
===================================================================
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3173,7 +3173,7 @@ gen_intermediate_code_internal(CPUState
cris_evaluate_flags (dc);
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(env->singlestep_enabled & SSTEP_DEBUG)) {
tcg_gen_movi_tl(env_pc, npc);
t_gen_raise_exception(EXCP_DEBUG);
} else {
Index: b/target-i386/translate.c
===================================================================
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2618,7 +2618,7 @@ static void gen_eob(DisasContext *s)
if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
tcg_gen_helper_0_0(helper_reset_inhibit_irq);
}
- if (s->singlestep_enabled) {
+ if (s->singlestep_enabled & SSTEP_DEBUG) {
tcg_gen_helper_0_0(helper_debug);
} else if (s->tf) {
tcg_gen_helper_0_0(helper_single_step);
Index: b/target-m68k/translate.c
===================================================================
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -871,7 +871,7 @@ static void gen_jmp_tb(DisasContext *s,
TranslationBlock *tb;
tb = s->tb;
- if (unlikely(s->singlestep_enabled)) {
+ if (unlikely(s->singlestep_enabled & SSTEP_DEBUG)) {
gen_exception(s, dest, EXCP_DEBUG);
} else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
(s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
@@ -2974,7 +2974,7 @@ gen_intermediate_code_internal(CPUState
!env->singlestep_enabled &&
(pc_offset) < (TARGET_PAGE_SIZE - 32));
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(env->singlestep_enabled & SSTEP_DEBUG)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
gen_flush_cc_op(dc);
Index: b/target-mips/translate.c
===================================================================
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7744,7 +7744,7 @@ gen_intermediate_code_internal (CPUState
break;
#endif
}
- if (env->singlestep_enabled) {
+ if (env->singlestep_enabled & SSTEP_DEBUG) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
} else {
Index: b/target-ppc/translate.c
===================================================================
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6319,7 +6319,7 @@ static always_inline int gen_intermediat
if (ctx.exception == POWERPC_EXCP_NONE) {
gen_goto_tb(&ctx, 0, ctx.nip);
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(env->singlestep_enabled & SSTEP_DEBUG)) {
gen_update_nip(&ctx, ctx.nip);
gen_op_debug();
}
Index: b/target-sh4/translate.c
===================================================================
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -161,7 +161,7 @@ static void gen_goto_tb(DisasContext * c
tcg_gen_exit_tb((long) tb + n);
} else {
gen_op_movl_imm_PC(dest);
- if (ctx->singlestep_enabled)
+ if (ctx->singlestep_enabled & SSTEP_DEBUG)
gen_op_debug();
tcg_gen_exit_tb(0);
}
@@ -173,7 +173,7 @@ static void gen_jump(DisasContext * ctx)
/* Target is not statically known, it comes necessarily from a
delayed jump as immediate jump are conditinal jumps */
gen_op_movl_delayed_pc_PC();
- if (ctx->singlestep_enabled)
+ if (ctx->singlestep_enabled & SSTEP_DEBUG)
gen_op_debug();
tcg_gen_exit_tb(0);
} else {
@@ -1251,7 +1251,7 @@ gen_intermediate_code_internal(CPUState
break;
#endif
}
- if (env->singlestep_enabled) {
+ if (env->singlestep_enabled & SSTEP_DEBUG) {
gen_op_debug();
} else {
switch (ctx.bstate) {
Index: b/vl.c
===================================================================
--- a/vl.c
+++ b/vl.c
@@ -7027,9 +7027,10 @@ void main_loop_wait(int timeout)
qemu_aio_poll();
if (vm_running) {
- if (likely(!(cur_cpu->singlestep_enabled & SSTEP_NOTIMER)))
- qemu_run_timers(&active_timers[QEMU_TIMER_VIRTUAL],
- qemu_get_clock(vm_clock));
+ if (likely(!(cur_cpu->singlestep_enabled &
+ (SSTEP_NOTIMER | SSTEP_INTERNAL))))
+ qemu_run_timers(&active_timers[QEMU_TIMER_VIRTUAL],
+ qemu_get_clock(vm_clock));
/* run dma transfers, if any */
DMA_run();
}
Index: b/gdbstub.c
===================================================================
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -77,7 +77,7 @@ typedef struct GDBState {
/* By default use no IRQs and no timers while single stepping so as to
* make single stepping like an ICE HW step.
*/
-static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
+static int sstep_flags = SSTEP_DEBUG | SSTEP_NOIRQ | SSTEP_NOTIMER;
#ifdef CONFIG_USER_ONLY
/* XXX: This is not thread safe. Do we care? */
@@ -1174,7 +1174,7 @@ static int gdb_handle_packet(GDBState *s
if (!strcmp(p,"qemu.sstepbits")) {
/* Query Breakpoint bit definitions */
sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
- SSTEP_ENABLE,
+ SSTEP_DEBUG,
SSTEP_NOIRQ,
SSTEP_NOTIMER);
put_packet(s, buf);
- [Qemu-devel] [PATCH 0/15] Enhance debugging support, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 8/15] Respect length of watchpoints, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 2/15] Introduce SSTEP_INTERNAL,
Jan Kiszka <=
- [Qemu-devel] [PATCH 12/15] Introduce BP_WATCHPOINT_HIT flag, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 5/15] Return appropriate watch message to gdb, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 6/15] Refactor and enhance break/watchpoint API - v5, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 14/15] Introduce BP_CPU as a breakpoint type, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 1/15] Convert remaining __builtin_expect to likely/unlikely, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 7/15] Extend mem_write_* to mem_access_*, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 13/15] Add debug exception hook, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 3/15] Replace CF_SINGLE_INSN with SSTEP_INTERNAL - v2, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 15/15] x86: Debug register emulation, Jan Kiszka, 2008/06/23
- [Qemu-devel] [PATCH 10/15] Remove premature memop TB terminations, Jan Kiszka, 2008/06/23