[Qemu-devel] Re: [4622] Fix for 32-bit MIPS.

[Richard Sandiford]

Hi Thiemo,

Thanks for applying the patches, and sorry for the fallout on 32-bit
targets from the DIV patch.

Thiemo Seufer <address@hidden> writes:
> @@ -1904,15 +1904,16 @@
>              {
>                  TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
>                  TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
> +                TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
>  
> -                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
> -                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
> -                tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]);
> -                tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
> -                tcg_gen_ext32s_tl(r_tmp1, r_tmp1);
> -                tcg_gen_ext32s_tl(r_tmp2, r_tmp2);
> -                gen_store_LO(r_tmp1, 0);
> -                gen_store_HI(r_tmp2, 0);
> +                tcg_gen_ext_tl_i64(r_tmp1, cpu_T[0]);
> +                tcg_gen_ext_tl_i64(r_tmp2, cpu_T[1]);
> +                tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2);
> +                tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
> +                tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
> +                tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
> +                gen_store_LO(cpu_T[0], 0);
> +                gen_store_HI(cpu_T[1], 0);
>              }
>              gen_set_label(l1);
>          }

This isn't quite right for 64-bit targets.  Both pairs of "ext32s"s
really were needed.  The input pair were needed so that we don't trigger
the SIGFPE for unpredictable cases in which the source operands are not
sign-extended.  (Should never happen, of course, but it's a pain if it
crashes the emulator.)  The output pair are needed so that the 32-bit
result is correctly sign-extended.  E.g., with the problem case of
0xffffffff80000000 / -1, the result is now 0x0000000080000000 instead
of 0xffffffff80000000.

In other words, I think we need both the ext32s_tl and the ext_tl_i64/
trunc_i64_tl operations.  Sorry for not picking this up in the original
submission.

Richard