Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[Thiemo Seufer]

M. Warner Losh wrote:
> In message: <address@hidden>
>             Paul Brook <address@hidden> writes:
> : > : > I know that Cavium/octeon board are MIPS CPU.
> : > :
> : > : Not really. They're MIPS with extra weirdness.
> : >
> : > All SoCs are MIPS with extra documented weirdness.  The OCTEON CPUs
> : > aren't documented in a public...
> : 
> : The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA. 
> : Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals.
> 
> Yes, they do use the noraml MIPS ISA.  It is a MIPS64r2 part.

AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr
with different instructions for unaligned load/stores. :-(


Thiemo