Re: [Qemu-devel] Alpha build failure: dyngen picking out a nameless symbol

[Blue Swirl]

On 11/14/07, Shaddy Baddah <address@hidden> wrote:
> Hi,
>
> I am building qemu from CVS, on a sun4u machine. I have used the
> following configure command to ensure a sun4m userland build:
>
> ../qemu/configure --prefix=/opt/qemu-cvs --sparc_cpu=v8
>
> I get the following message confirming the use of GCC 3:
>
> Looking for gcc 3.x
> Found "gcc-3.4"
>
> Eventually, I get the error I have included at the base of this email. I
> have attached the op.h generated. As you will be able to see from the
> line below, a nameless symbol is being referenced (after the &):
>
> op.h:24:    *(uint32_t *)(gen_code_ptr + 0) = ((*(uint32_t
> *)(gen_code_ptr + 0))  & ~0x3fffff)  | ((((long)(&) + 0) >> 10) & 0x3fffff);
>
> ^
> I've followed the dyngen code as best as I can, and AFAICT that code is
> right. The symbol referenced is nameless in the ELF symbol table.

The problem is in op_reset_FT0. Source is like this:
void OPPROTO glue(op_reset_FT, REG) (void)
{
    glue(FT, REG) = 0;
    RETURN();
}

The code generated for op_reset_FT0 is like this:
        .section        .rodata.cst8,"aM",@progbits,8
        .align 8
.LLC0:
        .long   0
        .long   0
        .section        ".text"
        .align 4
        .global op_reset_FT0
        .type   op_reset_FT0, #function
        .proc   020
op_reset_FT0:
.LLFB152:
        .loc 1 30 0
        !#PROLOGUE# 0
        !#PROLOGUE# 1
        .loc 1 31 0
        sethi   %hi(.LLC0), %g1
        ldd     [%g1+%lo(.LLC0)], %f8
        std     %f8, [%g6+1176]
        .loc 1 32 0
        nop
        retl
        nop
.LLFE152:
        .size   op_reset_FT0, .-op_reset_FT0

So gcc puts the zero constant to .rodata.cst8 and generates code to
load the zero value from this location. This method is not supported
by dyngen for Sparc, but ARM uses similar method for all (?)
constants.