Re: [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions

[Fabrice Bellard]

Aurelien Jarno wrote:
> Hi,
>
> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
> sdl and sdr instructions are not correctly implemented. In case of 
> exception the BadVAddr register gets the aligned address instead of the
> unaligned original address.
>
> In addition to that, the store instructions are generating the wrong
> exception, AdEl instead of AdEs, because the current implementation 
> first do a load.
>
> The patch below fixes that by accessing the bytes one by one, starting
> by the unaligned original address.
> [...]

It would be a lot more efficient to add specific code in the MIPS 
exception handling.

Fabrice.