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Re: [Qemu-devel] [MIPS][PATCH] Fix mfc0 and dmtc0 instructions on MIPS64

From: Thiemo Seufer
Subject: Re: [Qemu-devel] [MIPS][PATCH] Fix mfc0 and dmtc0 instructions on MIPS64
Date: Sun, 13 May 2007 15:37:49 +0100
User-agent: Mutt/1.5.13 (2006-08-11)

Aurelien Jarno wrote:
> Hi all,
> The patch below fixes the mfc0 and dmtc0 instructions for the 
> MIPS64 target:
> - The mfc0 instruction should return the 32 lowest bits of the 
>   coprocessor 0 register sign extended to 64-bit.

Agreed, and I think it doess already. (The places where you added
casts read fron 32bit wide registers anyway.)

> - The mtc0 instruction should do the same as the dmtc0 instruction for 
>   64-bit coprocessor registers instead of copying only the low 32 bits.

I'm not entirely sure about this, but it feels wrong, as mtc0 should
have the same behaviour as on 32bit CPUs. What prompted the change here?

> - The XContest register does not exists on MIPS32 CPU.

Indeed, but simply not wiring up the instruction decoding for 32bit
should be good enough, no need to #ifdef everything.


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