|Subject:||Re: [Qemu-devel] ARM CPU Speed simulated by Qemu?|
|Date:||Tue, 12 Sep 2006 16:21:21 +0200|
|User-agent:||Thunderbird 22.214.171.124 (X11/20060812)|
Paul Brook wrote:
IMHO a benchmarking setup that doesn't reliably correspond to real system performance is worse than useless.
Agreed. So let's see what's needed to get a reliably corresponding system. I'm interested in three layers: CPU, hard disk and network.
Networking is the simplest, I think. I would need to be able to define throughput and latency and be able to simulate network collisions (i.e. packet loss percentage).
Emulating a hard disk is already more complicated. One could likewise define throughput and latency (= avg. seek time). But in most cases that would not be sufficient, because depending on the head position, seek time may vary wildly. Thus more like a rotation speed and head position emulation is necessary. Most disks today also have different zones with varying data density (more sectors on the outer tracks). And last but not least, there are caches in most drives...
Now, CPUs is where I have only a vague idea of what would be needed to simulate. I know there are up to three levels of caches and main memory, which all have different access times. The CPU itself has a pipeline and branch prediction and such which could invalidate the contents of pipeline up to a given point (of branching).
I think the most time consuming operation which should be properly simulated is memory access. For this to work properly, all levels of caches must be emulated, too.
How much do misses on the branch prediction level cost? How much pipeline interlocks? I don't think those would be _that_ dramatic. Since today's compilers are said to be optimizing quite well...
I agree that implementing all of that would be a significant amount of work, already. What else do I miss?
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