[Qemu-devel] [PATCH 1/3] Fix MIPS counter / compare interrupt

[Ralf Baechle]

The count / compare interrupt is wired to the CPU's internal interrupt
controller, not a PIC.

 hw/mips_r4k.c        |   10 ++++++++--
 target-mips/helper.c |   12 +++++++++++-
 2 files changed, 19 insertions(+), 3 deletions(-)

Index: qemu-mips/hw/mips_r4k.c
===================================================================
--- qemu-mips.orig/hw/mips_r4k.c
+++ qemu-mips/hw/mips_r4k.c
@@ -72,7 +75,8 @@ void cpu_mips_store_count (CPUState *env
 void cpu_mips_store_compare (CPUState *env, uint32_t value)
 {
     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
-    pic_set_irq(5, 0);
+    cpu_single_env->CP0_Cause &= ~0x00008000;
+    cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 }
 
 static void mips_timer_cb (void *opaque)
@@ -86,7 +90,8 @@ static void mips_timer_cb (void *opaque)
     }
 #endif
     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
-    pic_set_irq(5, 1);
+    cpu_single_env->CP0_Cause |= 0x00008000;
+    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 }
 
 void cpu_mips_clock_init (CPUState *env)