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Re: [Qemu-devel] [patch] gcc4 host support
From: |
Paul Brook |
Subject: |
Re: [Qemu-devel] [patch] gcc4 host support |
Date: |
Tue, 17 May 2005 21:46:30 +0100 |
User-agent: |
KMail/1.7.2 |
On Monday 16 May 2005 10:41, David Woodhouse wrote:
> On Wed, 2005-05-11 at 22:04 +0100, Paul Brook wrote:
> > My solution is to search the function for the "ret" instruction and
> > replace them with a jmp to the next block of code. On RISC targets this
> > would be easy.
>
> About this easy, in fact...
>...
> +
> + if (get32((uint32_t *)p) == 0x4e800020) {
> + blr_addr = p;
> + copy_size = p_end - p_start;
> + break;
> + }
You probably want to scan the whole function to check there aren't multiple
blr instructions, and throw an error if there are.
Other than that it looks ok to me.
Paul
- [Qemu-devel] [patch] gcc4 host support, Paul Brook, 2005/05/11
- Re: [Qemu-devel] [patch] gcc4 host support, David Woodhouse, 2005/05/16
- Re: [Qemu-devel] [patch] gcc4 host support,
Paul Brook <=
- Re: [Qemu-devel] [patch] gcc4 host support, John Hogerhuis, 2005/05/18
- Re: [Qemu-devel] [patch] gcc4 host support, Paul Brook, 2005/05/18
- Re: [Qemu-devel] [patch] gcc4 host support, David Woodhouse, 2005/05/18
- Re: [Qemu-devel] [patch] gcc4 host support, Paul Brook, 2005/05/18
- Re: [Qemu-devel] [patch] gcc4 host support, jeebs, 2005/05/18
- Re: [Qemu-devel] [patch] gcc4 host support, Ian Rogers, 2005/05/18
- Re: [Qemu-devel] [patch] gcc4 host support, Paul Brook, 2005/05/18