Re: [Qemu-devel] Solaris (9 and 10) supported on 0.6.1?

[Juergen Keil]

> I just pulled the source from CVS and applied the mentioned patch

Which patch?


> but had no luck (tried running qemu both
> with and without -isa). It keeps bumping on the "cannot mount root"
> error and reboot automatically again and again.

Are you trying to install Solaris 9 x86, or Solaris 10 x86?

Looking at your screenshot image, it seems you're trying to install Solaris 9
x86.

I do see some slight differences between Solaris 9 and 10 x86, and qemu-cvs:

Solaris 9 x86 & qemu cvs "-pci" crashes with pci-ide timeout and abort 
error messages (with exactly the error messages that you've got).

Solaris 9 x86 & qemu cvs "-isa" works.

Solaris 9 x86 & qemu cvs "-pci" + attached ide.c patch works, and uses
ide hdd dma transfers. 


Solaris 10 x86 & qemu cvs "-pci" works, but complains that the ide controller
is not busmaster dma capable, so ide hdd pio transfers are used instead of
dma transfers.

Solaris 10 x86 & qemu cvs "-pci" + attached ide.c patch detects a pci busmaster
capable ide controller and uses ide dma transfers.


(Note tested by me, but reported to work:)  Solaris "next" x86 & qemu cvs
"-pci" + attached ide.c patch is able to use dma transfers for both the
ide hdd and the ide atapi cdrom.

Index: hw/ide.c
===================================================================
RCS file: /cvsroot/qemu/qemu/hw/ide.c,v
retrieving revision 1.32
diff -u -B -r1.32 ide.c
--- hw/ide.c    2 Dec 2004 20:20:21 -0000       1.32
+++ hw/ide.c    22 Apr 2005 08:11:08 -0000
@@ -361,6 +361,9 @@
 } PCIIDEState;
 
 static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb);
+static int ide_atapi_cmd_read_dma_cb(IDEState *s, 
+                                     target_phys_addr_t phys_addr, 
+                                     int transfer_size1);
 
 static void padstr(char *str, const char *src, int len)
 {
@@ -419,7 +422,7 @@
     put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
     put_le16(p + 51, 0x200); /* PIO transfer cycle */
     put_le16(p + 52, 0x200); /* DMA transfer cycle */
-    put_le16(p + 53, 1 | 1 << 2); /* words 54-58,88 are valid */
+    put_le16(p + 53, 1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 are valid */
     put_le16(p + 54, s->cylinders);
     put_le16(p + 55, s->heads);
     put_le16(p + 56, s->sectors);
@@ -430,6 +433,8 @@
         put_le16(p + 59, 0x100 | s->mult_sectors);
     put_le16(p + 60, s->nb_sectors);
     put_le16(p + 61, s->nb_sectors >> 16);
+    put_le16(p + 63, 0x07 | 0x4 << 8); /* Multiword DMA supported/selected */
+    put_le16(p + 64, 0x03); /* PIO modes 3,4 supported */
     put_le16(p + 80, (1 << 1) | (1 << 2));
     put_le16(p + 82, (1 << 14));
     put_le16(p + 83, (1 << 14));
@@ -437,8 +442,8 @@
     put_le16(p + 85, (1 << 14));
     put_le16(p + 86, 0);
     put_le16(p + 87, (1 << 14));
-    put_le16(p + 88, 0x1f | (1 << 13));
-    put_le16(p + 93, 1 | (1 << 14) | 0x2000 | 0x4000);
+    put_le16(p + 88, 0x3f /*| 0x20 << 8*/); /* UltraDMA modes 
supported/selected */
+    put_le16(p + 93, 1 | (1 << 1) | (1 << 3) | (1 << 13) | (1 << 14));
 }
 
 static void ide_atapi_identify(IDEState *s)
@@ -458,10 +463,10 @@
     padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
     padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
     put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
-    put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
-    put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
-    put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
-    put_le16(p + 64, 1); /* PIO modes */
+    put_le16(p + 49, 1 << 8 | 1 << 9); /* DMA and LBA supported */
+    put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
+    put_le16(p + 63, 0x07 | 0x4 << 8); /* Multiword DMA supported/selected */
+    put_le16(p + 64, 0x03); /* PIO modes 3,4 supported */
     put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
     put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
     put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
@@ -471,6 +476,7 @@
     put_le16(p + 72, 30); /* in ns */
 
     put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
+    put_le16(p + 88, 0x3f /*| 0x20 << 8*/); /* UltraDMA modes 
supported/selected */
 }
 
 static void ide_set_signature(IDEState *s)
@@ -500,6 +506,10 @@
 static inline void ide_set_irq(IDEState *s)
 {
     if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
+       BMDMAState *bm = s->bmdma;
+       if(bm)
+           bm->status |= BM_STATUS_INT;
+
 #ifdef TARGET_PPC
         if (s->openpic) 
             openpic_set_irq(s->openpic, s->irq, 1);
@@ -890,8 +900,13 @@
     s->elementary_transfer_size = 0;
     s->io_buffer_index = 0;
 
-    s->status = READY_STAT;
-    ide_atapi_cmd_reply_end(s);
+    if (s->atapi_dma) {
+       s->status = READY_STAT | DRQ_STAT;
+       ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
+    } else {
+       s->status = READY_STAT;
+       ide_atapi_cmd_reply_end(s);
+    }
 }
 
 /* start a CD-CDROM read command */
@@ -919,14 +934,18 @@
     while (transfer_size > 0) {
         if (s->packet_transfer_size <= 0)
             break;
-        len = s->cd_sector_size - s->io_buffer_index;
-        if (len <= 0) {
-            /* transfert next data */
-            cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
-            s->lba++;
-            s->io_buffer_index = 0;
-            len = s->cd_sector_size;
-        }
+       if (s->lba == -1)
+           len = s->packet_transfer_size;
+       else {
+           len = s->cd_sector_size - s->io_buffer_index;
+           if (len <= 0) {
+               /* transfert next data */
+               cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
+               s->lba++;
+               s->io_buffer_index = 0;
+               len = s->cd_sector_size;
+           }
+       }
         if (len > transfer_size)
             len = transfer_size;
         cpu_physical_memory_write(phys_addr, 
@@ -2191,6 +2210,12 @@
     ide_init2(&d->ide_if[2], 16, hd_table[2], hd_table[3]);
 }
 
+
+// PCI 0x04: command(word), 0x06(word): status
+#define PCI_COMMAND_IOACCESS                0x0001
+#define PCI_COMMAND_MEMACCESS               0x0002
+#define PCI_COMMAND_BUSMASTER               0x0004
+
 /* hd_table must contain 4 block drivers */
 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
@@ -2208,6 +2233,9 @@
     pci_conf[0x01] = 0x80;
     pci_conf[0x02] = 0x10;
     pci_conf[0x03] = 0x70;
+    pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS \
+       | PCI_COMMAND_BUSMASTER;
+    pci_conf[0x09] = 0x8a; // programming interface = PCI_IDE bus master is 
supported
     pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
     pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
     pci_conf[0x0e] = 0x00; // header_type