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[Qemu-commits] [qemu/qemu] 80ac95: target/arm: Use extract2 for EXTR
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 80ac95: target/arm: Use extract2 for EXTR |
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Date: |
Fri, 24 May 2019 03:05:52 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 80ac954c369e7e61bd1ed00cef07b63e11f9c734
https://github.com/qemu/qemu/commit/80ac954c369e7e61bd1ed00cef07b63e11f9c734
Author: Richard Henderson <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use extract2 for EXTR
This is, after all, how we implement extract2 in tcg/aarch64.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 87eb65a3c45c788a309986d48170a54a0d1c0705
https://github.com/qemu/qemu/commit/87eb65a3c45c788a309986d48170a54a0d1c0705
Author: Richard Henderson <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Simplify BFXIL expansion
The mask implied by the extract is redundant with the one
implied by the deposit. Also, fix spelling of BFXIL.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2f143d3ad1c05e91cf2cdf5de06d59a80a95e6c8
https://github.com/qemu/qemu/commit/2f143d3ad1c05e91cf2cdf5de06d59a80a95e6c8
Author: Alistair Francis <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Fix vector operation segfault
Commit 89e68b575 "target/arm: Use vector operations for saturation"
causes this abort() when booting QEMU ARM with a Cortex-A15:
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>,
s=<optimized out>) at ./target/arm/translate.c:6673
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>,
insn=<optimized out>) at ./target/arm/translate.c:6386
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at
./target/arm/translate.c:9289
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510,
cpu=<optimized out>) at ./target/arm/translate.c:13612
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580
<arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized
out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
7 0x00005555559d10d4 in gen_intermediate_code (address@hidden, address@hidden
<code_gen_buffer+126091347>, address@hidden) at ./target/arm/translate.c:13901
8 0x00005555558d06b9 in tb_gen_code (address@hidden, pc=3067096216, cs_base=0,
flags=192, cflags=-16252928, address@hidden) at ./accel/tcg/translate-all.c:1736
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1,
last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at
./accel/tcg/cpu-exec.c:407
10 0x00005555558ce467 in cpu_exec (address@hidden) at ./accel/tcg/cpu-exec.c:728
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at
./cpus.c:1735
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (address@hidden) at
./cpus.c:1709
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at
./util/qemu-thread-posix.c:502
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
This patch ensures that we don't hit the abort() in the second switch
case in disas_neon_data_insn() as we will return from the first case.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 807420f0b0a71cc7cf38abe06321b5777091e47d
https://github.com/qemu/qemu/commit/807420f0b0a71cc7cf38abe06321b5777091e47d
Author: Peter Maydell <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M include/hw/arm/arm.h
M include/hw/timer/armv7m_systick.h
Log Message:
-----------
arm: Move system_clock_scale to armv7m_systick.h
The system_clock_scale global is used only by the armv7m systick
device; move the extern declaration to the armv7m_systick.h header,
and expand the comment to explain what it is and that it should
ideally be replaced with a different approach.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 55bb1a55c72b249afa32dc1d788f230bf6a0a70d
https://github.com/qemu/qemu/commit/55bb1a55c72b249afa32dc1d788f230bf6a0a70d
Author: Peter Maydell <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/arm-semi.c
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/kvm.c
M target/arm/kvm32.c
M target/arm/kvm64.c
Log Message:
-----------
arm: Remove unnecessary includes of hw/arm/arm.h
The hw/arm/arm.h header now only includes declarations relating
to boot.c code, so it is only needed by Arm board or SoC code.
Remove some unnecessary inclusions of it from target/arm files
and from hw/intc/armv7m_nvic.c.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 12ec8bd51e81a025a444585359f019f49b57a702
https://github.com/qemu/qemu/commit/12ec8bd51e81a025a444585359f019f49b57a702
Author: Peter Maydell <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/arm/armsse.c
M hw/arm/armv7m.c
M hw/arm/aspeed.c
M hw/arm/boot.c
M hw/arm/collie.c
M hw/arm/exynos4210.c
M hw/arm/exynos4_boards.c
M hw/arm/highbank.c
M hw/arm/integratorcp.c
M hw/arm/mainstone.c
M hw/arm/microbit.c
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/arm/msf2-soc.c
M hw/arm/msf2-som.c
M hw/arm/musca.c
M hw/arm/musicpal.c
M hw/arm/netduino2.c
M hw/arm/nrf51_soc.c
M hw/arm/nseries.c
M hw/arm/omap1.c
M hw/arm/omap2.c
M hw/arm/omap_sx1.c
M hw/arm/palm.c
M hw/arm/raspi.c
M hw/arm/realview.c
M hw/arm/spitz.c
M hw/arm/stellaris.c
M hw/arm/stm32f205_soc.c
M hw/arm/strongarm.c
M hw/arm/tosa.c
M hw/arm/versatilepb.c
M hw/arm/vexpress.c
M hw/arm/virt.c
M hw/arm/xilinx_zynq.c
M hw/arm/xlnx-versal.c
M hw/arm/z2.c
M include/hw/arm/allwinner-a10.h
R include/hw/arm/arm.h
M include/hw/arm/aspeed_soc.h
M include/hw/arm/bcm2836.h
A include/hw/arm/boot.h
M include/hw/arm/fsl-imx25.h
M include/hw/arm/fsl-imx31.h
M include/hw/arm/fsl-imx6.h
M include/hw/arm/fsl-imx6ul.h
M include/hw/arm/fsl-imx7.h
M include/hw/arm/virt.h
M include/hw/arm/xlnx-versal.h
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
arm: Rename hw/arm/arm.h to hw/arm/boot.h
The header file hw/arm/arm.h now includes only declarations
relating to hw/arm/boot.c functionality. Rename it accordingly,
and adjust its header comment.
The bulk of this commit was created via
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
In a few cases we can just delete the #include:
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
include/hw/arm/bcm2836.h did not require it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 8b7fbd6c36b868ad16cb7065dbba93ac342479af
https://github.com/qemu/qemu/commit/8b7fbd6c36b868ad16cb7065dbba93ac342479af
Author: Peter Maydell <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
In ich_vmcr_write() we enforce "writes of BPR fields to less than
their minimum sets them to the minimum" by doing a "read vbpr and
write it back" operation. A typo here meant that we weren't handling
writes to these fields correctly, because we were reading from VBPR0
but writing to VBPR1.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 09380dd131eadf31a7ff286e766892b9a1ec6e31
https://github.com/qemu/qemu/commit/09380dd131eadf31a7ff286e766892b9a1ec6e31
Author: Peter Maydell <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 67c9b59f8e6a938945f317b10d9544da9605a8f6
https://github.com/qemu/qemu/commit/67c9b59f8e6a938945f317b10d9544da9605a8f6
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/arm/exynos4_boards.c
Log Message:
-----------
hw/arm/exynos4: Remove unuseful debug code
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e12a0dd28d07be556a1ce1543a9c1e281f931e8c
https://github.com/qemu/qemu/commit/e12a0dd28d07be556a1ce1543a9c1e281f931e8c
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/arm/exynos4_boards.c
Log Message:
-----------
hw/arm/exynos4: Use the IEC binary prefix definitions
It eases code review, unit is explicit.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 59520dc65e5ddb7bdc1a8b7bedd4b58eb76b068b
https://github.com/qemu/qemu/commit/59520dc65e5ddb7bdc1a8b7bedd4b58eb76b068b
Author: Guenter Roeck <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210.
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
/ {
soc: soc {
amba {
pdma0: address@hidden {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: address@hidden {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: address@hidden {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};
};
Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMD: Do not set default qdev properties, create the controllers in the SoC
rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 98e4f4fdb8ea05d840f51f47125924c2bb9df2df
https://github.com/qemu/qemu/commit/98e4f4fdb8ea05d840f51f47125924c2bb9df2df
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-05-23 (Thu, 23 May 2019)
Changed paths:
M hw/arm/exynos4210.c
M hw/arm/exynos4_boards.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: ceac83e9ba724d915353d740a11ca08670deea59
https://github.com/qemu/qemu/commit/ceac83e9ba724d915353d740a11ca08670deea59
Author: Peter Maydell <address@hidden>
Date: 2019-05-24 (Fri, 24 May 2019)
Changed paths:
M hw/arm/armsse.c
M hw/arm/armv7m.c
M hw/arm/aspeed.c
M hw/arm/boot.c
M hw/arm/collie.c
M hw/arm/exynos4210.c
M hw/arm/exynos4_boards.c
M hw/arm/highbank.c
M hw/arm/integratorcp.c
M hw/arm/mainstone.c
M hw/arm/microbit.c
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/arm/msf2-soc.c
M hw/arm/msf2-som.c
M hw/arm/musca.c
M hw/arm/musicpal.c
M hw/arm/netduino2.c
M hw/arm/nrf51_soc.c
M hw/arm/nseries.c
M hw/arm/omap1.c
M hw/arm/omap2.c
M hw/arm/omap_sx1.c
M hw/arm/palm.c
M hw/arm/raspi.c
M hw/arm/realview.c
M hw/arm/spitz.c
M hw/arm/stellaris.c
M hw/arm/stm32f205_soc.c
M hw/arm/strongarm.c
M hw/arm/tosa.c
M hw/arm/versatilepb.c
M hw/arm/vexpress.c
M hw/arm/virt.c
M hw/arm/xilinx_zynq.c
M hw/arm/xlnx-versal.c
M hw/arm/z2.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/armv7m_nvic.c
M include/hw/arm/allwinner-a10.h
R include/hw/arm/arm.h
M include/hw/arm/aspeed_soc.h
M include/hw/arm/bcm2836.h
A include/hw/arm/boot.h
M include/hw/arm/exynos4210.h
M include/hw/arm/fsl-imx25.h
M include/hw/arm/fsl-imx31.h
M include/hw/arm/fsl-imx6.h
M include/hw/arm/fsl-imx6ul.h
M include/hw/arm/fsl-imx7.h
M include/hw/arm/virt.h
M include/hw/arm/xlnx-versal.h
M include/hw/arm/xlnx-zynqmp.h
M include/hw/timer/armv7m_systick.h
M target/arm/arm-semi.c
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/kvm.c
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190523'
into staging
target-arm queue:
* exynos4210: QOM'ify the Exynos4210 SoC
* exynos4210: Add DMA support for the Exynos4210
* arm_gicv3: Fix writes to ICC_CTLR_EL3
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
* target/arm: Fix vector operation segfault
* target/arm: Minor improvements to BFXIL, EXTR
# gpg: Signature made Thu 23 May 2019 15:22:55 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190523:
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
hw/arm/exynos4210: Add DMA support for the Exynos4210
hw/arm/exynos4: Use the IEC binary prefix definitions
hw/arm/exynos4: Remove unuseful debug code
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
arm: Rename hw/arm/arm.h to hw/arm/boot.h
arm: Remove unnecessary includes of hw/arm/arm.h
arm: Move system_clock_scale to armv7m_systick.h
target/arm: Fix vector operation segfault
target/arm: Simplify BFXIL expansion
target/arm: Use extract2 for EXTR
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/8dc7fd56dd4f...ceac83e9ba72
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