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[Qemu-commits] [qemu/qemu] 2cca53: s390x: Use cpu_to_be64 in SIGP STORE
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 2cca53: s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL ST... |
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Date: |
Mon, 04 Mar 2019 06:29:24 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 2cca53fd5c11460b81cb043dc273129d7b3a2ab8
https://github.com/qemu/qemu/commit/2cca53fd5c11460b81cb043dc273129d7b3a2ab8
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/helper.c
Log Message:
-----------
s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUS
As we will support vector instructions soon, and vector registers are
stored in 64bit host chunks, let's use cpu_to_be64. Same applies to the
guarded storage control block.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Christian Borntraeger <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 257619be4243d9b7f12b619027d9a5c2f2270350
https://github.com/qemu/qemu/commit/257619be4243d9b7f12b619027d9a5c2f2270350
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/helper.c
Log Message:
-----------
s390x: use a QEMU-style typedef + name for SIGP save area struct
Convert this to QEMU style.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Acked-by: Christian Borntraeger <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 9693379ba25631422709c09b48bfbbedfb602bae
https://github.com/qemu/qemu/commit/9693379ba25631422709c09b48bfbbedfb602bae
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/excp_helper.c
M target/s390x/internal.h
Log Message:
-----------
s390x/tcg: Save vregs to extended mchk save area
If we have vector registers and the designation is not zero, we have
to try to write the vector registers. If the designation is zero or
if storing fails, we must not indicate validity. s390_build_validity_mcic()
automatically already sets validity if the vector instruction facility
is installed.
As long as we don't support the guarded-storage facility, the alignment
and size of the area is always 1024 bytes.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 374b78e37029b05f7ee2f40d0d0aabf5b5b03ce0
https://github.com/qemu/qemu/commit/374b78e37029b05f7ee2f40d0d0aabf5b5b03ce0
Author: Tony Krowiak <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M hw/s390x/ap-bridge.c
M hw/vfio/ap.c
Log Message:
-----------
s390x/vfio-ap: Implement hot plug/unplug of vfio-ap device
Introduces hot plug/unplug support for the vfio-ap device.
To hot plug a vfio-ap device using the QEMU device_add command:
(qemu) device_add vfio-ap,sysfsdev=$path-to-mdev
Where $path-to-mdev is the absolute path to the mediated matrix device
to which AP resources to be used by the guest have been assigned.
A vfio-ap device can be hot plugged only if:
1. A vfio-ap device has not been attached to the virtual machine's ap-bus
via the QEMU command line or a prior hot plug action.
2. The guest was started with the CPU model feature for AP enabled
(e.g., -cpu host,ap=on)
To hot unplug a vfio-ap device using the QEMU device_del command:
(qemu) device_del vfio-ap,sysfsdev=$path-to-mdev
Where $path-to-mdev is the absolute path to the mediated matrix device
specified when the vfio-ap device was attached to the virtual machine's
ap-bus.
A vfio-ap device can be hot unplugged only if:
1. A vfio-ap device has been attached to the virtual machine's ap-bus
via the QEMU command line or a prior hot plug action.
2. The guest was started with the CPU model feature for AP enabled
(e.g., -cpu host,ap=on)
Please note that a hot plug handler is not necessary for the vfio-ap device
because the AP matrix configuration for the guest is performed by the
kernel device driver when the vfio-ap device is realized. The vfio-ap device
represents a VFIO mediated device created in the host sysfs for use by a guest.
The mdev device is configured with an AP matrix (i.e., adapters and domains) via
its sysfs attribute interfaces prior to starting the guest or plugging a vfio-ap
device in. When the device is realized, a file descriptor is opened on the mdev
device which results in a callback to the vfio_ap kernel device driver. The
device driver then configures the AP matrix in the guest's SIE state description
from the AP matrix assigned via the mdev device's sysfs interfaces. The AP
devices will be created for the guest when the AP bus running on the guest
subsequently performs its periodic scan for AP devices.
The qdev_simple_device_unplug_cb() callback function is used for the same
reaons; namely, the vfio_ap kernel device driver will perform the AP resource
de-configuration for the guest when the vfio-ap device is unplugged. When the
vfio-ap device is unrealized, the mdev device file descriptor is closed which
results in a callback to the vfio_ap kernel device driver. The device driver
then clears the AP matrix configuration in the guest's SIE state description
and resets all of the affected queues. The AP devices created for the guest
will be removed when the AP bus running on the guest subsequently performs
its periodic scan and finds there are no longer any AP resources assigned to the
guest.
Signed-off-by: Tony Krowiak <address@hidden>
Reviewed-by: Pierre Morel <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Reviewed-by: Halil Pasic <address@hidden>
Tested-by: Pierre Morel <address@hidden>
Message-Id: <address@hidden>
[CH: adapt to changed qbus_set_hotplug_handler() signature]
Signed-off-by: Cornelia Huck <address@hidden>
Commit: bac03ec72f1b1e3336a5c7e14a89e61312ab925a
https://github.com/qemu/qemu/commit/bac03ec72f1b1e3336a5c7e14a89e61312ab925a
Author: Tony Krowiak <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M docs/vfio-ap.txt
Log Message:
-----------
s390x/vfio-ap: document hot plug/unplug of vfio-ap device
Let's update the vfio-ap.txt document to include the hot plug/unplug
support.
Signed-off-by: Tony Krowiak <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 5cf955066515df9f948947fce668a05ca6164e14
https://github.com/qemu/qemu/commit/5cf955066515df9f948947fce668a05ca6164e14
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/insn-format.def
Log Message:
-----------
s390x/tcg: RXE has an optional M3 field
Will be needed, so add it to the format description.
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 076081ec8c9d8f1662ebb0ef6dc2d3dfd1c09eea
https://github.com/qemu/qemu/commit/076081ec8c9d8f1662ebb0ef6dc2d3dfd1c09eea
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Simplify disassembler operands initialization
Let's simplify initialization to 0.
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: ffdd8ebb79a6533913a1fbcf0aa12ef107842202
https://github.com/qemu/qemu/commit/ffdd8ebb79a6533913a1fbcf0aa12ef107842202
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Clarify terminology in vec_reg_offset()
We will use s390x speak "Element Size" (es) for MO_8 == 0, MO_16 == 1
... Simple rename of variables.
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 27197fec128d5ee97ec060f99b95df2c48668783
https://github.com/qemu/qemu/commit/27197fec128d5ee97ec060f99b95df2c48668783
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Factor out vec_full_reg_offset()
We'll use that a lot along with gvec helpers, to calculate the start
address of a vector.
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 2a1cf844520748a18740a905e6286987d3e4e62d
https://github.com/qemu/qemu/commit/2a1cf844520748a18740a905e6286987d3e4e62d
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()
Also properly wrap in 24bit mode. While at it, convert the comment (and
drop the comment about fundamental TCG optimizations).
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 86b59624c4aa2a383aca7a1798740779ac8967ce
https://github.com/qemu/qemu/commit/86b59624c4aa2a383aca7a1798740779ac8967ce
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/insn-data.def
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP
Nice trick to load a 32 bit value into vector element 0 (32 bit element
size) from memory, zeroing out element1. The short HFP to long HFP
conversion really only is a shift.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 6d9303322ed9580ff6c61e38a427b549410464c7
https://github.com/qemu/qemu/commit/6d9303322ed9580ff6c61e38a427b549410464c7
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/cc_helper.c
M target/s390x/helper.c
M target/s390x/insn-data.def
M target/s390x/internal.h
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY
Use a new CC helper to calculate the CC lazily if needed. While the
PoP mentions that "A 32-bit unsigned binary integer" is placed into the
first operand, there is no word telling that the other 32 bits (high
part) are left untouched. Maybe the other 32-bit are unpredictable.
So store 64 bit for now.
Bit magic courtesy of Richard.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: fc7cc951b606c9ea9044cd4b96cbdf9720761c64
https://github.com/qemu/qemu/commit/fc7cc951b606c9ea9044cd4b96cbdf9720761c64
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Fix TEST DATA CLASS instructions
Let's detect normal and denormal ("subnormal") numbers reliably. Also
test for quiet NaN's. As only one class is possible, test common cases
first.
While at it, use a better check to test for the mask bits in the data
class mask. The data class mask has 12 bits, whereby bit 0 is the
leftmost bit and bit 11 the rightmost bit. In the PoP an easy to read
table with the numbers is provided for the VECTOR FP TEST DATA CLASS
IMMEDIATE instruction, the table for TEST DATA CLASS is more confusing
as it is based on 64 bit values.
Factor the checks out into separate functions, as they will also be
needed for floating point vector instructions. We can use a makro to
generate the functions.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 3af471f9152b8e84534f8b0ff303b5f0a5ced819
https://github.com/qemu/qemu/commit/3af471f9152b8e84534f8b0ff303b5f0a5ced819
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Fix rounding from float128 to uint64_t/uint32_t
Let's use the proper conversion functions now that we have them.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 4b70fc54975b3b09eeec30be33419bd03456fe45
https://github.com/qemu/qemu/commit/4b70fc54975b3b09eeec30be33419bd03456fe45
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/internal.h
Log Message:
-----------
s390x/tcg: Factor out conversion of softfloat exceptions
We want to reuse that function in vector instruction context. While at it,
cleanup the code, using defines for magic values and avoiding the
handcrafted bit conversion.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: fcb9e9f2a1b229b834e4133f626c4f40b43f7b9d
https://github.com/qemu/qemu/commit/fcb9e9f2a1b229b834e4133f626c4f40b43f7b9d
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Fix parts of IEEE exception handling
Many things are wrong and some parts cannot be fixed yet. Fix what we
can fix easily and add two FIXMEs:
The fpc flags are not updated in case an exception is actually injected.
Inexact exceptions have to be handled separately, as they are the only
exceptions that can coexist with underflows and overflows.
I reread the horribly complicated chapters in the PoP at least 5 times
and hope I got it right.
For references:
- z14 PoP, 9-18, "IEEE Exceptions"
- z14 PoP, 19-9, Figure 19-8
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 6d6ad1d14e2fdbc693524dbd721ef33d0adb9473
https://github.com/qemu/qemu/commit/6d6ad1d14e2fdbc693524dbd721ef33d0adb9473
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Hide IEEE underflows in some scenarios
IEEE underflows are not reported when the mask bit is off and we don't
also have an inexact exception.
z14 PoP, 9-20, "IEEE Underflow":
An IEEE-underflow exception is recognized for an
IEEE target when the tininess condition exists and
either: (1) the IEEE-underflow mask bit in the FPC
register is zero and the result value is inexact, or (2)
the IEEE-underflow mask bit in the FPC register is
one.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: f66a0ecf233cae4cf170ccd1c339776b5b344775
https://github.com/qemu/qemu/commit/f66a0ecf233cae4cf170ccd1c339776b5b344775
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Refactor SET FPC AND SIGNAL handling
We can directly work on the uint64_t value, no need for a temporary
uint32_t value.
Also cleanup and shorten the comments.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 8772bbe4e7cc7d67792440b0e7ea819e3cc930db
https://github.com/qemu/qemu/commit/8772bbe4e7cc7d67792440b0e7ea819e3cc930db
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Fix simulated-IEEE exceptions
The trap is triggered based on priority of the enabled signaling flags.
Only overflow and underflow allow a concurrent inexact exception.
z14 PoP, 9-33, Figure 9-21
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 2aea83c6728f5006e07e4f148c2798441683fe86
https://github.com/qemu/qemu/commit/2aea83c6728f5006e07e4f148c2798441683fe86
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/helper.h
Log Message:
-----------
s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modes
We already forward the 3 bits correctly in the translation functions. We
also have to handle them properly and check for specification
exceptions.
Setting an invalid rounding mode (BFP only, all DFP rounding modes)
results in a specification exception. Setting unassigned bits in the
fpc, results in a specification exception.
This fixes LOAD FPC (AND SIGNAL), SET FPC (AND SIGNAL). Also for,
SET BFP ROUNDING MODE, 3-bit rounding mode is now explicitly checked.
Note: TCG_CALL_NO_WG is required for sfpc handler, as we now inject
exceptions.
We won't be modeling abscence of the "floating-point extension facility"
for now, not necessary as most take the facility for granted without
checking.
z14 PoP, 9-23, "LOAD FPC"
When the floating-point extension facility is
installed, bits 29-31 of the second operand must
specify a valid BFP rounding mode and bits 6-7,
14-15, 24, and 28 must be zero; otherwise, a
specification exception is recognized.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: b9c737f58e82bf89efaa4a04ab3f730342c06a3a
https://github.com/qemu/qemu/commit/b9c737f58e82bf89efaa4a04ab3f730342c06a3a
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE
Let's split handling of BFP/DFP rounding mode configuration. Also,
let's not reuse the sfpc handler, use a separate handler so we can
properly check for specification exceptions for SRNMB.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: c0ee7015fdd8b8a4134a468a7ab9d825ca114a76
https://github.com/qemu/qemu/commit/c0ee7015fdd8b8a4134a468a7ab9d825ca114a76
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/internal.h
Log Message:
-----------
s390x/tcg: Refactor saving/restoring the bfp rounding mode
We want to reuse this in the context of vector instructions. So use
better matching names and introduce s390_restore_bfp_rounding_mode().
While at it, add proper newlines.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: cf97f9ff94662433f997c40d023b90e2506655de
https://github.com/qemu/qemu/commit/cf97f9ff94662433f997c40d023b90e2506655de
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Prepare for IEEE-inexact-exception control (XxC)
Some instructions allow to suppress IEEE inexact exceptions.
z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions"
IEEE-inexact-exception control (XxC): Bit 1 of
the M4 field is the XxC bit. If XxC is zero, recogni-
tion of IEEE-inexact exception is not suppressed;
if XxC is one, recognition of IEEE-inexact excep-
tion is suppressed.
Especially, handling for overflow/unerflow remains as is, inexact is
reported along
z14 PoP, 9-23, "Suppression of Certain IEEE Exceptions"
For example, the IEEE-inexact-exception control (XxC)
has no effect on the DXC; that is, the DXC for IEEE-
overflow or IEEE-underflow exceptions along with the
detail for exact, inexact and truncated, or inexact and
incremented, is reported according to the actual con-
dition.
Follow up patches will wire it correctly up for the applicable
instructions.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: dce0a58fd6427e4c9d1399ced70a04276db71a5f
https://github.com/qemu/qemu/commit/dce0a58fd6427e4c9d1399ced70a04276db71a5f
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Implement XxC and checks for most FP instructions
With the floating-point extension facility
- CONVERT FROM LOGICAL
- CONVERT TO LOGICAL
- CONVERT TO FIXED
- CONVERT FROM FIXED
- LOAD FP INTEGER
have both, a rounding mode specification and the inexact-exception control
(XxC). Other instructions will be handled separatly.
Check for valid rounding modes and forward also the XxC (via m4). To avoid
a lot of boilerplate code and changes to the helpers, combine both, the
m3 and m4 field in a combined 32 bit TCG variable. Perform checks at
a central place, taking in account if the m3 or m4 field was ignore
before the floating-point extension facility was introduced.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: bdcfcd445dd4f07e4df5345f1cdd0da5a5e6ba5f
https://github.com/qemu/qemu/commit/bdcfcd445dd4f07e4df5345f1cdd0da5a5e6ba5f
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDED
With the floating-point extension facility, LOAD ROUNDED has
a rounding mode specification and the inexact-exception control (XxC).
Handle them just like e.g. LOAD FP INTEGER.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: b12b103ecdfa0a5a7466a57fc1e55fc00afcd0db
https://github.com/qemu/qemu/commit/b12b103ecdfa0a5a7466a57fc1e55fc00afcd0db
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/fpu_helper.c
Log Message:
-----------
s390x/tcg: Handle all rounding modes overwritten by BFP instructions
"round to nearest with ties away from 0" maps to float_round_ties_away.
"round to prepare for shorter precision" maps to float_round_to_odd.
As all instructions properly check for valid rounding modes in translate.c
we can add an assert. Fix one missing empty line.
Cc: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: df192fbc517a0954dda644282e52ba943e22ec18
https://github.com/qemu/qemu/commit/df192fbc517a0954dda644282e52ba943e22ec18
Author: David Hildenbrand <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M target/s390x/gen-features.c
Log Message:
-----------
s390x: Add floating-point extension facility to "qemu" cpu model
The floating-point extension facility implemented certain changes to
BFP, HFP and DFP instructions.
As we don't implement HFP/DFP, we can ignore those completely. Related
to BFP, the changes include
- SET BFP ROUNDING MODE (SRNMB) instruction
- BFP-rounding-mode field in the FPC register is changed to 3 bits
- CONVERT FROM LOGICAL instructions
- CONVERT TO LOGICAL instructions
- Changes (rounding mode + XxC) added to
-- CONVERT TO FIXED
-- CONVERT FROM FIXED
-- LOAD FP INTEGER
-- LOAD ROUNDED
-- DIVIDE TO INTEGER
For TCG, we don't implement DIVIDE TO INTEGER, and it is harder to
implement, so skip that. Also, as we don't implement PFPO, we can skip
changes to that as well. The other parts are now implemented, we can
indicate the facility.
z14 PoP mentions that "The floating-point extension facility is installed
in the z/Architecture architectural mode. When bit 37 is one, bit 42 is
also one.", meaning that the DFP (decimal-floating-point) facility also
has to be indicated. We can ignore that for now.
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 1ba530a4ecba6015d52d8f392fd327cfa07bc37a
https://github.com/qemu/qemu/commit/1ba530a4ecba6015d52d8f392fd327cfa07bc37a
Author: Peter Maydell <address@hidden>
Date: 2019-03-04 (Mon, 04 Mar 2019)
Changed paths:
M docs/vfio-ap.txt
M hw/s390x/ap-bridge.c
M hw/vfio/ap.c
M target/s390x/cc_helper.c
M target/s390x/excp_helper.c
M target/s390x/fpu_helper.c
M target/s390x/gen-features.c
M target/s390x/helper.c
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/insn-format.def
M target/s390x/internal.h
M target/s390x/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190304' into staging
s390x updates:
- tcg: support the floating-point extension facility
- vfio-ap: support hot(un)plug of vfio-ap device
- fixes + cleanups
# gpg: Signature made Mon 04 Mar 2019 11:55:39 GMT
# gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg: issuer "address@hidden"
# gpg: Good signature from "Cornelia Huck <address@hidden>" [unknown]
# gpg: aka "Cornelia Huck <address@hidden>" [full]
# gpg: aka "Cornelia Huck <address@hidden>" [full]
# gpg: aka "Cornelia Huck <address@hidden>" [unknown]
# gpg: aka "Cornelia Huck <address@hidden>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF
* remotes/cohuck/tags/s390x-20190304: (27 commits)
s390x: Add floating-point extension facility to "qemu" cpu model
s390x/tcg: Handle all rounding modes overwritten by BFP instructions
s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDED
s390x/tcg: Implement XxC and checks for most FP instructions
s390x/tcg: Prepare for IEEE-inexact-exception control (XxC)
s390x/tcg: Refactor saving/restoring the bfp rounding mode
s390x/tcg: Check for exceptions in SET BFP ROUNDING MODE
s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modes
s390x/tcg: Fix simulated-IEEE exceptions
s390x/tcg: Refactor SET FPC AND SIGNAL handling
s390x/tcg: Hide IEEE underflows in some scenarios
s390x/tcg: Fix parts of IEEE exception handling
s390x/tcg: Factor out conversion of softfloat exceptions
s390x/tcg: Fix rounding from float128 to uint64_t/uint32_t
s390x/tcg: Fix TEST DATA CLASS instructions
s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARY
s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFP
s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()
s390x/tcg: Factor out vec_full_reg_offset()
s390x/tcg: Clarify terminology in vec_reg_offset()
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/1d31f1872b33...1ba530a4ecba
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