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[Qemu-commits] [qemu/qemu] 36d820: target/arm: Fix validation of 32-bit


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 36d820: target/arm: Fix validation of 32-bit address space...
Date: Tue, 29 Jan 2019 13:38:51 +0000 (UTC)

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 36d820af0eddf4fc6a533579b052d8f0085a9fb8
      
https://github.com/qemu/qemu/commit/36d820af0eddf4fc6a533579b052d8f0085a9fb8
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix validation of 32-bit address spaces for aa32

When tsz == 0, aarch32 selects the address space via exclusion,
and there are no "top_bits" remaining that require validation.

Fixes: ba97be9f4a4
Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7e3f122367ec56ea2e8b7313cef82162eb7538c7
      
https://github.com/qemu/qemu/commit/7e3f122367ec56ea2e8b7313cef82162eb7538c7
  Author: Thomas Roth <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: v8m: Ensure IDAU is respected if SAU is disabled

The current behavior of v8m_security_lookup in helper.c only checks whether the
IDAU specifies a higher security if the SAU is enabled. If SAU.ALLNS is set to
1, this will lead to addresses being treated as non-secure, even though the
IDAU indicates that they must be secure.

This patch changes the behavior to also check the IDAU if the SAU is currently
disabled.

(This brings the behaviour here into line with the v8M Arm ARM
SecurityCheck() pseudocode.)

Signed-off-by: Thomas Roth <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added pseudocode ref to the commit message, fixed comment style]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ab65eed3f82b57459ef8c45f75a89241f16cbad8
      
https://github.com/qemu/qemu/commit/ab65eed3f82b57459ef8c45f75a89241f16cbad8
  Author: Luc Michel <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0

a TID or PID value means "any thread" (resp. "any process"). This commit
fixes the different combinations when at least one value is 0.

When both are 0, the function now returns the first attached CPU,
instead of the CPU with TID 1, which is not necessarily attached or even
existent.

When PID is specified but TID is 0, the function returns the first CPU
in the process, or NULL if the process does not exist or is not
attached.

In other cases, it returns the corresponding CPU, while ignoring the PID
check when PID is 0.

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9d68bf564ecd038c8939b9779f4b6d62a01ce6f3
      
https://github.com/qemu/qemu/commit/9d68bf564ecd038c8939b9779f4b6d62a01ce6f3
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/arm/microbit.c
    M hw/i2c/Makefile.objs
    A hw/i2c/microbit_i2c.c
    M include/hw/arm/nrf51.h
    M include/hw/arm/nrf51_soc.h
    A include/hw/i2c/microbit_i2c.h

  Log Message:
  -----------
  arm: Stub out NRF51 TWI magnetometer/accelerometer detection

Recent microbit firmwares panic if the TWI magnetometer/accelerometer
devices are not detected during startup.  We don't implement TWI (I2C)
so let's stub out these devices just to let the firmware boot.

Signed-off by: Steffen Görtz <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: fixed comment style]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b36356f69941bcda47ac3d97c2b05757728575c9
      
https://github.com/qemu/qemu/commit/b36356f69941bcda47ac3d97c2b05757728575c9
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M tests/microbit-test.c

  Log Message:
  -----------
  tests/microbit-test: add TWI stub device test

This test verifies that we read back the expected I2C WHO_AM_I register
values for the accelerometer/magnetometer.

Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ea7a5330b79523540ba776c529b09dc8cf3fa0c5
      
https://github.com/qemu/qemu/commit/ea7a5330b79523540ba776c529b09dc8cf3fa0c5
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Use correct attrs in cpu_memory_rw_debug()

In the softmmu version of cpu_memory_rw_debug(), we ask the
CPU for the attributes to use for the virtual memory access,
and we correctly use those to identify the address space
index. However, we were not passing them in to the
address_space_write_rom() and address_space_rw() functions.

The effect of this was that a memory access from the gdbstub
to a device which had behaviour that was sensitive to the
memory attributes (such as some ARMv8M NVIC registers) was
incorrectly always performed as if non-secure, rather than
using the right security state for the CPU's current state.

Fixes: https://bugs.launchpad.net/qemu/+bug/1812091

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Stefano Garzarella <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: f454a54f3bf95920d236ad893344141085db061a
      
https://github.com/qemu/qemu/commit/f454a54f3bf95920d236ad893344141085db061a
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write

In cpu_signal_handler() for aarch64 hosts, currently we parse
the faulting instruction to see if it is a load or a store.
Since the 3.16 kernel (~2014), the kernel has provided us with
the syndrome register for a fault, which includes the WnR bit.
Use this instead if it is present, only falling back to
instruction parsing if not.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: c8de3f5fd696db0e0a16062de4b9c75252401e4e
      
https://github.com/qemu/qemu/commit/c8de3f5fd696db0e0a16062de4b9c75252401e4e
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: update microbit ARM board files

New source files were added without corresponding ./MAINTAINERS file
entries.  Let's get things up to date.

Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bf8d09694ccc07487cd73d7562081fdaec3370c8
      
https://github.com/qemu/qemu/commit/bf8d09694ccc07487cd73d7562081fdaec3370c8
  Author: Aaron Lindsay OS <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Don't clear supported PMU events when initializing PMCEID1

A bug was introduced during a respin of:

        commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a
        target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0

This patch introduced two calls to get_pmceid() during CPU
initialization - one each for PMCEID0 and PMCEID1. In addition to
building the register values, get_pmceid() clears an internal array
mapping event numbers to their implementations (supported_event_map)
before rebuilding it. This is an optimization since much of the logic is
shared. However, since it was called twice, the contents of
supported_event_map reflect only the events in PMCEID1 (the second call
to get_pmceid()).

Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back
into a single function call, and name it more appropriately since it is
doing more than simply generating the contents of the PMCEID[01]
registers.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 047be4ed24b3a408acccf9316d619477c06cca42
      
https://github.com/qemu/qemu/commit/047be4ed24b3a408acccf9316d619477c06cca42
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M exec.c
    M include/exec/memory.h

  Log Message:
  -----------
  memory: add memory_region_flush_rom_device()

ROM devices go via MemoryRegionOps->write() callbacks for write
operations and do not dirty/invalidate that memory.  Device emulation
must be able to mark memory ranges that have been modified internally
(e.g. using memory_region_get_ram_ptr()).

Introduce the memory_region_flush_rom_device() API for this purpose.

Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: fix block comment style]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6c90a82c9358c77017b94d67c1a3fa24e0500e07
      
https://github.com/qemu/qemu/commit/6c90a82c9358c77017b94d67c1a3fa24e0500e07
  Author: Julia Suvorova <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M tests/libqtest.c
    M tests/libqtest.h

  Log Message:
  -----------
  tests/libqtest: Introduce qtest_init_with_serial()

Run qtest with a socket that connects QEMU chardev and test code.

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7cf19e7352fc213011d5a051535b28ec696e02d1
      
https://github.com/qemu/qemu/commit/7cf19e7352fc213011d5a051535b28ec696e02d1
  Author: Julia Suvorova <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M tests/microbit-test.c

  Log Message:
  -----------
  tests/microbit-test: Make test independent of global_qtest

Using of global_qtest is not required here. Let's replace functions like
readl() with the corresponding qtest_* counterparts.

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 46a6603ba6ea545b92c9e53b19998ade97ed8b05
      
https://github.com/qemu/qemu/commit/46a6603ba6ea545b92c9e53b19998ade97ed8b05
  Author: Julia Suvorova <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M tests/microbit-test.c

  Log Message:
  -----------
  tests/microbit-test: Check nRF51 UART functionality

Some functional tests for:
    Basic reception/transmittion
    Suspending
    INTEN* registers

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b94e809d3e4dbfa986d7c19fd2072c313b9a3a36
      
https://github.com/qemu/qemu/commit/b94e809d3e4dbfa986d7c19fd2072c313b9a3a36
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M scripts/checkpatch.pl

  Log Message:
  -----------
  checkpatch: Don't emit spurious warnings about block comments

In checkpatch we attempt to check for and warn about
block comments which start with /* or /** followed by a
non-blank. Unfortunately a bug in the regex meant that
we would incorrectly warn about comments starting with
"/**" with no following text:

  git show 9813dc6ac3954d58ba16b3920556f106f97e1c67|./scripts/checkpatch.pl -
  WARNING: Block comments use a leading /* on a separate line
  #34: FILE: tests/libqtest.h:233:
  +/**

The sequence "/\*\*?" was intended to match either "/*" or "/**",
but Perl's semantics for '?' allow it to backtrack and try the
"matches 0 chars" option if the "matches 1 char" choice leads to
a failure of the rest of the regex to match.  Switch to "/\*\*?+"
which uses what perlre(1) calls the "possessive" quantifier form:
this means that if it matches the "/**" string it will not later
backtrack to matching just the "/*" prefix.

The other end of the regex is also wrong: it is attempting
to check for "/* or /** followed by something that isn't
just whitespace", but [ \t]*.+[ \t]* will match on pure
whitespace. This is less significant but means that a line
with just a comment-starter followed by trailing whitespace
will generate an incorrect warning about block comment style
as well as the correct error about trailing whitespace which
a different checkpatch test emits.

Fixes: 8c06fbdf36bf4d ("scripts/checkpatch.pl: Enforce multiline comment 
syntax")
Reported-by: Thomas Huth <address@hidden>
Reported-by: Eric Blake <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Message-id: address@hidden


  Commit: e5b517536cb47989236fbfe5bd69e644a1ff8467
      
https://github.com/qemu/qemu/commit/e5b517536cb47989236fbfe5bd69e644a1ff8467
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs

If we aren't going to create any RPUs, then don't create the
rpu-cluster unit. This allows us to add an assertion to the
cluster object that it contains at least one CPU, which helps
to avoid bugs in creating clusters and putting CPUs in them.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: b617ca9223353624000017e2fa499d6d3296b293
      
https://github.com/qemu/qemu/commit/b617ca9223353624000017e2fa499d6d3296b293
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: fix default read value

0xFFFFFFFF should be returned for non implemented registers.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 597d6bb3e8a93c4c0670df93f07c321ae84d2930
      
https://github.com/qemu/qemu/commit/597d6bb3e8a93c4c0670df93f07c321ae84d2930
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: define registers for all possible CS

The model should expose one control register per possible CS. When
testing the validity of the register number in the read operation,
replace 's->num_cs' by 'ctrl->max_slaves' which represents the maximum
number of flash devices a controller can handle.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9149af2a2d3609507959bb17b74a35c3cebc5f66
      
https://github.com/qemu/qemu/commit/9149af2a2d3609507959bb17b74a35c3cebc5f66
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Add dummy data register

The SMC controllers have a register containing the byte that will be
used as dummy output. It can be modified by software.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f95c4bffdc4c53b29f89762cab4adc5a43f95daf
      
https://github.com/qemu/qemu/commit/f95c4bffdc4c53b29f89762cab4adc5a43f95daf
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: snoop SPI transfers to fake dummy cycles

The m25p80 models dummy cycles using byte transfers. This works well
when the transfers are initiated by the QEMU model of a SPI controller
but when these are initiated by the OS, it breaks emulation.

Snoop the SPI transfer to catch commands requiring dummy cycles and
replace them with byte transfers compatible with the m25p80 model.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fa434424652ecfd3efba39e11ff7a1a560943abd
      
https://github.com/qemu/qemu/commit/fa434424652ecfd3efba39e11ff7a1a560943abd
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it

Currently the cluster implementation doesn't have any constraints
on the ordering of realizing the TYPE_CPU_CLUSTER and populating it
with child objects. We want to impose a constraint that realize
must happen only after all the child objects are added, so move
the realize of rpu_cluster. (The apu_cluster is already
realized after child population.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 7ea7b9ad532e59c3efbcabff0e3484f4df06104c
      
https://github.com/qemu/qemu/commit/7ea7b9ad532e59c3efbcabff0e3484f4df06104c
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M hw/cpu/cluster.c
    M include/hw/cpu/cluster.h
    M include/qom/cpu.h
    M qom/cpu.c

  Log Message:
  -----------
  qom/cpu: Add cluster_index to CPUState

For TCG we want to distinguish which cluster a CPU is in, and
we need to do it quickly. Cache the cluster index in the CPUState
struct, by having the cluster object set cpu->cluster_index for
each CPU child when it is realized.

This means that board/SoC code must add all CPUs to the cluster
before realizing the cluster object. Regrettably QOM provides no
way to prevent adding children to a realized object and no way for
the parent to be notified when a new child is added to it, so
we don't have any way to enforce/assert this constraint; all
we can do is document it in a comment. We can at least put in a
check that the cluster contains at least one CPU, which should
catch the typical cases of "realized cluster too early" or
"forgot to parent the CPUs into it".

The restriction on how many clusters can exist in the system
is imposed by TCG code which will be added in a subsequent commit,
but the check to enforce it in cluster.c fits better in this one.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden


  Commit: f7b78602fdc6c6e4befc90159da8e93900b4bcb1
      
https://github.com/qemu/qemu/commit/f7b78602fdc6c6e4befc90159da8e93900b4bcb1
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M accel/tcg/translate-all.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  accel/tcg: Add cluster number to TCG TB hash

Include the cluster number in the hash we use to look
up TBs. This is important because a TB that is valid
for one cluster at a given physical address and set
of CPU flags is not necessarily valid for another:
the two clusters may have different views of physical
memory, or may have different CPU features (eg FPU
present or absent).

We put the cluster number in the high 8 bits of the
TB cflags. This gives us up to 256 clusters, which should
be enough for anybody. If we ever need more, or need
more bits in cflags for other purposes, we could make
tb_hash_func() take more data (and expand qemu_xxhash7()
to qemu_xxhash8()).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 46f5abc0a2566ac3dc954eeb62fd625f0eaca120
      
https://github.com/qemu/qemu/commit/46f5abc0a2566ac3dc954eeb62fd625f0eaca120
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index

Now we're keeping the cluster index in the CPUState, we don't
need to jump through hoops in gdb_get_cpu_pid() to find the
associated cluster object.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: b4fbe1f65a4769c09e6bf2d79fc84360f840f40e
      
https://github.com/qemu/qemu/commit/b4fbe1f65a4769c09e6bf2d79fc84360f840f40e
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-29 (Tue, 29 Jan 2019)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/cpu-exec.c
    M accel/tcg/translate-all.c
    M accel/tcg/user-exec.c
    M exec.c
    M gdbstub.c
    M hw/arm/microbit.c
    M hw/arm/xlnx-zynqmp.c
    M hw/cpu/cluster.c
    M hw/i2c/Makefile.objs
    A hw/i2c/microbit_i2c.c
    M hw/ssi/aspeed_smc.c
    M include/exec/exec-all.h
    M include/exec/memory.h
    M include/hw/arm/nrf51.h
    M include/hw/arm/nrf51_soc.h
    M include/hw/cpu/cluster.h
    A include/hw/i2c/microbit_i2c.h
    M include/hw/ssi/aspeed_smc.h
    M include/qom/cpu.h
    M qom/cpu.c
    M scripts/checkpatch.pl
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M tests/libqtest.c
    M tests/libqtest.h
    M tests/microbit-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190129' 
into staging

target-arm queue:
 * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced 
in ba97be9f4a4)
 * v8m: Ensure IDAU is respected if SAU is disabled
 * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
 * exec.c: Use correct attrs in cpu_memory_rw_debug()
 * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
 * target/arm: Don't clear supported PMU events when initializing PMCEID1
 * memory: add memory_region_flush_rom_device()
 * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
 * tests/microbit-test: extend testing of microbit devices
 * checkpatch: Don't emit spurious warnings about block comments
 * aspeed/smc: misc bug fixes
 * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
 * xlnx-zynqmp: Realize cluster after putting RPUs in it
 * accel/tcg: Add cluster number to TCG TB hash so differently configured
   CPUs don't pick up cached TBs for the wrong kind of CPU

# gpg: Signature made Tue 29 Jan 2019 11:59:10 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190129: (23 commits)
  gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
  accel/tcg: Add cluster number to TCG TB hash
  qom/cpu: Add cluster_index to CPUState
  hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
  aspeed/smc: snoop SPI transfers to fake dummy cycles
  aspeed/smc: Add dummy data register
  aspeed/smc: define registers for all possible CS
  aspeed/smc: fix default read value
  xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
  checkpatch: Don't emit spurious warnings about block comments
  tests/microbit-test: Check nRF51 UART functionality
  tests/microbit-test: Make test independent of global_qtest
  tests/libqtest: Introduce qtest_init_with_serial()
  memory: add memory_region_flush_rom_device()
  target/arm: Don't clear supported PMU events when initializing PMCEID1
  MAINTAINERS: update microbit ARM board files
  accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
  exec.c: Use correct attrs in cpu_memory_rw_debug()
  tests/microbit-test: add TWI stub device test
  arm: Stub out NRF51 TWI magnetometer/accelerometer detection
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3a183e330dbd...b4fbe1f65a47



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