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[Qemu-commits] [qemu/qemu] 2431a4: target/mips: Add two missing breaks f


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 2431a4: target/mips: Add two missing breaks for NM_LLWPE a...
Date: Tue, 30 Oct 2018 05:02:15 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2431a422d325c1832d77dd64fa3135ec303b00de
      
https://github.com/qemu/qemu/commit/2431a422d325c1832d77dd64fa3135ec303b00de
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases

Coverity found two fallthroughs that miss break statement. Fix them.

Revieved-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: eb5559f67dc8dc12335dd996877bb6daaea32eb2
      
https://github.com/qemu/qemu/commit/eb5559f67dc8dc12335dd996877bb6daaea32eb2
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Introduce MXU registers

Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: a031ac61619294ae473a78d1834e757fad8b59e5
      
https://github.com/qemu/qemu/commit/a031ac61619294ae473a78d1834e757fad8b59e5
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/mips-defs.h

  Log Message:
  -----------
  target/mips: Define a bit for MXU in insn_flags

Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: eab0bdb07cbed1131be2d1f541059c7b96b05e32
      
https://github.com/qemu/qemu/commit/eab0bdb07cbed1131be2d1f541059c7b96b05e32
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Amend MXU instruction opcodes

Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 0a348b9a4e115deb28856e650b8fe5277e291c23
      
https://github.com/qemu/qemu/commit/0a348b9a4e115deb28856e650b8fe5277e291c23
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add and integrate MXU decoding engine placeholder

Provide the placeholder and add the invocation logic for MXU
decoding engine.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 03f400883a1dd92fac5b0d9127b38e34c9a722d7
      
https://github.com/qemu/qemu/commit/03f400883a1dd92fac5b0d9127b38e34c9a722d7
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add MXU decoding engine

Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: d67da3378624ee4b0215f5c9a16c19059f7f04da
      
https://github.com/qemu/qemu/commit/d67da3378624ee4b0215f5c9a16c19059f7f04da
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'

Add bit encoding for MXU accumulate add/subtract 1-bit pattern
'aptn1'.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: b70bb918e2f5063975ba845fb9456ada25e3db91
      
https://github.com/qemu/qemu/commit/b70bb918e2f5063975ba845fb9456ada25e3db91
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'

Add bit encoding for MXU accumulate add/subtract 2-bit pattern
'aptn2'.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 5bb29992397217ae7d09d2192c5b56aefaf6cd11
      
https://github.com/qemu/qemu/commit/5bb29992397217ae7d09d2192c5b56aefaf6cd11
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'

Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: a35723f4ce026ebad0c34f18ea874813799058f0
      
https://github.com/qemu/qemu/commit/a35723f4ce026ebad0c34f18ea874813799058f0
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add bit encoding for MXU operand getting pattern 'optn2'

Add bit encoding for MXU operand getting pattern 'optn2'.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 53f1131fde02ae49e1f794f811a60fda32c72dca
      
https://github.com/qemu/qemu/commit/53f1131fde02ae49e1f794f811a60fda32c72dca
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add bit encoding for MXU operand getting pattern 'optn3'

Add bit encoding for MXU operand getting pattern 'optn3'.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 11d56f61036091206f085e58cff72b6872911d3a
      
https://github.com/qemu/qemu/commit/11d56f61036091206f085e58cff72b6872911d3a
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of non-MXU MULL within MXU decoding engine

Add emulation of non-MXU MULL within MXU decoding engine.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 96992d1aa1b250c0fffc1ff2dad5e6e4f0b9815b
      
https://github.com/qemu/qemu/commit/96992d1aa1b250c0fffc1ff2dad5e6e4f0b9815b
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of MXU instructions S32I2M and S32M2I

Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 87860df5511b972f0234a6b2cfaad5227c79b6b4
      
https://github.com/qemu/qemu/commit/87860df5511b972f0234a6b2cfaad5227c79b6b4
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch

Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: be57bcdb2ed8a4b41be05c8dc42bdec5174f43d6
      
https://github.com/qemu/qemu/commit/be57bcdb2ed8a4b41be05c8dc42bdec5174f43d6
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of MXU instruction S8LDD

Add support for emulating the S8LDD MXU instruction.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 72c9bcf89c59ee1a8e4545069de3efcbeb4d4833
      
https://github.com/qemu/qemu/commit/72c9bcf89c59ee1a8e4545069de3efcbeb4d4833
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of MXU instruction D16MUL

Add support for emulating the D16MUL MXU instruction.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: e67915b4277932def37b15cf8434323d096edeaa
      
https://github.com/qemu/qemu/commit/e67915b4277932def37b15cf8434323d096edeaa
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of MXU instruction D16MAC

Add support for emulating the D16MAC MXU instruction.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: a9a4181bdbf9eea81d718894bda607bd01b00f5b
      
https://github.com/qemu/qemu/commit/a9a4181bdbf9eea81d718894bda607bd01b00f5b
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU

Adds support for emulating the Q8MUL and Q8MULSU MXU instructions.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 4ca837218c92139cb85d214a25d1d1bc3f7e044c
      
https://github.com/qemu/qemu/commit/4ca837218c92139cb85d214a25d1d1bc3f7e044c
  Author: Craig Janeczek <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Add emulation of MXU instructions S32LDD and S32LDDR

Add support for emulating the S32LDD and S32LDDR MXU instructions.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: e5bf8a08293a1c576f8b6094f4deae7bdafceade
      
https://github.com/qemu/qemu/commit/e5bf8a08293a1c576f8b6094f4deae7bdafceade
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Move MXU_EN check one level higher

Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 093ade12179b6a3f679c100c0fe2a0a7d72068ba
      
https://github.com/qemu/qemu/commit/093ade12179b6a3f679c100c0fe2a0a7d72068ba
  Author: Aleksandar Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Amend MXU ASE overview note

Add prefix, suffix, operation descriptions, and other corrections
and amendments to the comment that describes MXU ASE.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 3f8e8ac3314c0fcbd19983a81f676ac60d0ca5c8
      
https://github.com/qemu/qemu/commit/3f8e8ac3314c0fcbd19983a81f676ac60d0ca5c8
  Author: Stefan Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M include/elf.h

  Log Message:
  -----------
  elf: Define MIPS_ABI_FP_UNKNOWN macro

Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent
unknown fp_abi (based on kernel mips/include/asm/elf.h definition)

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>


  Commit: 74cfc704e539fd06dbb6f69ff9f6fb54dbfc0f1e
      
https://github.com/qemu/qemu/commit/74cfc704e539fd06dbb6f69ff9f6fb54dbfc0f1e
  Author: Stefan Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M linux-user/qemu.h

  Log Message:
  -----------
  linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields

Add MIPS specific image_info struct fields fp_abi and interp_fp_abi
to store executable and interpreter fp_abi values (based on kernel
struct arch_elf_state in mips/include/asm/elf.h).

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>


  Commit: 5dd0db52e6bc95c14892ae6e1e7b10f3d5979c1a
      
https://github.com/qemu/qemu/commit/5dd0db52e6bc95c14892ae6e1e7b10f3d5979c1a
  Author: Stefan Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Extract MIPS abiflags from ELF file

Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>


  Commit: c94cb6c94605346b8b15158a2f1b12782c0c41c5
      
https://github.com/qemu/qemu/commit/c94cb6c94605346b8b15158a2f1b12782c0c41c5
  Author: Stefan Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Read and set FP ABI value from MIPS abiflags

Set fp_abi and interp_fp_abi values to current fp_abi value read from
MIPS.abiflags.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>


  Commit: 0c1bbedc10e86ea9366b6af8c5520fafa3266b2f
      
https://github.com/qemu/qemu/commit/0c1bbedc10e86ea9366b6af8c5520fafa3266b2f
  Author: Stefan Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M linux-user/mips/cpu_loop.c

  Log Message:
  -----------
  linux-user: Determine the desired FPU mode from MIPS.abiflags

Floating-point mode is calculated from MIPS.abiflags FP ABI value
(based on kernel implementation). Illegal combinations are rejected.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>


  Commit: 64ea3d676d9447ecdb987deab5a1542ea088bd31
      
https://github.com/qemu/qemu/commit/64ea3d676d9447ecdb987deab5a1542ea088bd31
  Author: Stefan Markovic <address@hidden>
  Date:   2018-10-29 (Mon, 29 Oct 2018)

  Changed paths:
    M linux-user/mips/target_syscall.h
    M linux-user/mips64/target_syscall.h
    M linux-user/syscall.c

  Log Message:
  -----------
  linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations

Implement MIPS specific prctl() PR_SET_FP_MODE and PR_GET_FP_MODE emulation.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>


  Commit: 0bbba1665ca2e7f1c80d4797077fe57bad58898e
      
https://github.com/qemu/qemu/commit/0bbba1665ca2e7f1c80d4797077fe57bad58898e
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M include/elf.h
    M linux-user/elfload.c
    M linux-user/mips/cpu_loop.c
    M linux-user/mips/target_syscall.h
    M linux-user/mips64/target_syscall.h
    M linux-user/qemu.h
    M linux-user/syscall.c
    M target/mips/cpu.h
    M target/mips/mips-defs.h
    M target/mips/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/amarkovic/tags/mips-queue-october-2018-part-4' into staging

MIPS queue for October 2018, part 4

# gpg: Signature made Mon 29 Oct 2018 15:11:32 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-october-2018-part-4: (27 commits)
  linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations
  linux-user: Determine the desired FPU mode from MIPS.abiflags
  linux-user: Read and set FP ABI value from MIPS abiflags
  linux-user: Extract MIPS abiflags from ELF file
  linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields
  elf: Define MIPS_ABI_FP_UNKNOWN macro
  target/mips: Amend MXU ASE overview note
  target/mips: Move MXU_EN check one level higher
  target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
  target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
  target/mips: Add emulation of MXU instruction D16MAC
  target/mips: Add emulation of MXU instruction D16MUL
  target/mips: Add emulation of MXU instruction S8LDD
  target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
  target/mips: Add emulation of MXU instructions S32I2M and S32M2I
  target/mips: Add emulation of non-MXU MULL within MXU decoding engine
  target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
  target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
  target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
  target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/09ffed7eed62...0bbba1665ca2
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