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[Qemu-commits] [qemu/qemu] 8c2218: mailmap: Add an item for Yongbok Kim
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[Qemu-commits] [qemu/qemu] 8c2218: mailmap: Add an item for Yongbok Kim |
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Date: |
Fri, 19 Oct 2018 03:19:18 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 8c2218e313483eeb2748e46e6d742bc7d8c6081c
https://github.com/qemu/qemu/commit/8c2218e313483eeb2748e46e6d742bc7d8c6081c
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M .mailmap
Log Message:
-----------
mailmap: Add an item for Yongbok Kim
Yongbok Kim used two email adresses for QEMU contributions -
his company changed its ownership/name.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: a325197155521662711e5e0ffb52bbb77b90dcb6
https://github.com/qemu/qemu/commit/a325197155521662711e5e0ffb52bbb77b90dcb6
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M include/elf.h
Log Message:
-----------
elf: Fix PT_MIPS_XXX constants
Fix existing and add missing PT_MIPS_XXX constants in elf.h.
This is copied from kernel header arch/mips/include/asm/elf.h.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 967a1104d807506eee2e1f6f588827838ace70b0
https://github.com/qemu/qemu/commit/967a1104d807506eee2e1f6f588827838ace70b0
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M include/elf.h
Log Message:
-----------
elf: Add MIPS_ABI_FP_XXX constants
Add MIPS_ABI_FP_XXX constants to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: e46155810731ce22284725f53cb90f76615da92d
https://github.com/qemu/qemu/commit/e46155810731ce22284725f53cb90f76615da92d
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M include/elf.h
Log Message:
-----------
elf: Add Mips_elf_abiflags_v0 structure
Add Mips_elf_abiflags_v0 structure to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: f0a997c6b93cdb44b054a207475e528d01026f4f
https://github.com/qemu/qemu/commit/f0a997c6b93cdb44b054a207475e528d01026f4f
Author: Fredrik Noring <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M include/elf.h
Log Message:
-----------
elf: Fix comments to EF_MIPS_MACH_xxx constants
Regarding R5900 CPU, some sources indicate that the Emotion Engine
ISA/ASE was designed by Toshiba and licensed to Sony. Others sources
claim it was a joint effort. It therefore makes sense to refer to
the CPU as "Toshiba/Sony R5900".
Also, remove and "'s" in the line for some other CPU, for the sake
of consistency.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Reported-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: a2b9a10e94f5fc08f793b495bbb2b9416fafac83
https://github.com/qemu/qemu/commit/a2b9a10e94f5fc08f793b495bbb2b9416fafac83
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M linux-user/mips/target_syscall.h
M linux-user/mips64/target_syscall.h
Log Message:
-----------
linux-user: Add MIPS-specific prctl() options
Add MIPS-specific prctl() options TARGET_PR_SET_FP_MODE and
TARGET_PR_SET_FP_MODE. These values are essentially copied from
linux kernel header include/uapi/linux/prctl.h.
This is done in a way consistent with a similar case of
aarch64-specific prctl() options TARGET_PR_SVE_SET_VL and
TARGET_PR_SVE_GET_VL.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 5b702ffd42190698b08de683ed6cd1527457e3d4
https://github.com/qemu/qemu/commit/5b702ffd42190698b08de683ed6cd1527457e3d4
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: Add infrastructure for handling MIPS-specific prctl()
Add infrastructure for handling MIPS-specific prctl(). This is,
for now, just an empty placeholder. The real handling will be
implemented in subsequent patches.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: a86d421e18d58b32d6eaba1e79160e2b4e5a0a6c
https://github.com/qemu/qemu/commit/a86d421e18d58b32d6eaba1e79160e2b4e5a0a6c
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
Log Message:
-----------
target/mips: Add a comment with an overview of CP0 registers
Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 50e7edc5ac25af2faaacd1f91e177c7de7d696c3
https://github.com/qemu/qemu/commit/50e7edc5ac25af2faaacd1f91e177c7de7d696c3
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
Log Message:
-----------
target/mips: Add a comment before each CP0 register section in cpu.h
Add a comment before each CP0 register section in CPUMIPSState
definition, thus visually separating these sections.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: b158d449bbfe71bb203fdce978a4a33c38a4e821
https://github.com/qemu/qemu/commit/b158d449bbfe71bb203fdce978a4a33c38a4e821
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add basic description of MXU ASE
Add a comment that contains a basic description of MXU ASE.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 1d0e663c5f25345a6702d8a83c051b83f3462299
https://github.com/qemu/qemu/commit/1d0e663c5f25345a6702d8a83c051b83f3462299
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add assembler mnemonics list for MXU ASE
Add a comment that contains a list all MXU instructions,
expressed in assembler mnemonics.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 9ef5bff97b0d033e20446c83fc61bae7c054b03e
https://github.com/qemu/qemu/commit/9ef5bff97b0d033e20446c83fc61bae7c054b03e
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add organizational chart of MXU ASE
Add a comment that contains an organizational chart of MXU ASE
instructions.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 8bacd1ffc702c35d34ccd29b1a20c0273c9759cb
https://github.com/qemu/qemu/commit/8bacd1ffc702c35d34ccd29b1a20c0273c9759cb
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add opcode values of MXU ASE
Add opcode values for all instructions in MXU ASE.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: f9c9cd63e3dd84c5f052deec880ec92046bbe305
https://github.com/qemu/qemu/commit/f9c9cd63e3dd84c5f052deec880ec92046bbe305
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/translate.c
Log Message:
-----------
target/mips: Increase 'supported ISAs/ASEs' flag holder size
Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 45ebdd24c3de158890ce390df39855a891e80701
https://github.com/qemu/qemu/commit/45ebdd24c3de158890ce390df39855a891e80701
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
Distribute bits 56-63 vendor-specific ASEs as follows:
- bits 0-31 MIPS base instruction sets
- bits 32-47 MIPS ASEs
- bits 48-55 vendor-specific base instruction sets
- bits 56-63 vendor-specific ASEs
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 6208f09441dcf8d142ff0e1624ef12da298776a4
https://github.com/qemu/qemu/commit/6208f09441dcf8d142ff0e1624ef12da298776a4
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Add bit definitions for DSP R3 ASE
Add DSP R3 ASE related bit definition for insn_flags and hflags.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 59e781fbf13a2dede15437d055b09d7ea120dcac
https://github.com/qemu/qemu/commit/59e781fbf13a2dede15437d055b09d7ea120dcac
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/internal.h
M target/mips/translate.c
M target/mips/translate_init.inc.c
Log Message:
-----------
target/mips: Add availability control for DSP R3 ASE
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 908f6be1b9cbc270470230f805d6f7474ab3178d
https://github.com/qemu/qemu/commit/908f6be1b9cbc270470230f805d6f7474ab3178d
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
M target/mips/translate_init.inc.c
Log Message:
-----------
target/mips: Improve DSP R2/R3-related naming
Do following replacements:
ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2
MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()
and several other similar minor replacements.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 49735f76db25bf10f57973d5249f17151b801760
https://github.com/qemu/qemu/commit/49735f76db25bf10f57973d5249f17151b801760
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add CP0 Config2 to DisasContext
Add field corresponding to CP0 Config2 to DisasContext. This is
needed for availability control via Config2 bits.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6
https://github.com/qemu/qemu/commit/5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6
Author: Yongbok Kim <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/machine.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Add CP0 PWBase register
Add PWBase register (CP0 Register 5, Select 5).
The PWBase register contains the Page Table Base virtual address.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: fa75ad1459f4f6abbeb6d375a812dfad61320f58
https://github.com/qemu/qemu/commit/fa75ad1459f4f6abbeb6d375a812dfad61320f58
Author: Yongbok Kim <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/helper.h
M target/mips/machine.c
M target/mips/op_helper.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Add CP0 PWField register
Add PWField register (CP0 Register 5, Select 6).
The PWField register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
MIPS64:
BDI (37..32) - Base Directory index
GDI (29..24) - Global Directory index
UDI (23..18) - Upper Directory index
MDI (17..12) - Middle Directory index
PTI (11..6 ) - Page Table index
PTEI ( 5..0 ) - Page Table Entry shift
MIPS32:
GDW (29..24) - Global Directory index
UDW (23..18) - Upper Directory index
MDW (17..12) - Middle Directory index
PTW (11..6 ) - Page Table index
PTEW ( 5..0 ) - Page Table Entry shift
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 20b28ebc49945583d7191b57755cfd92433de9ff
https://github.com/qemu/qemu/commit/20b28ebc49945583d7191b57755cfd92433de9ff
Author: Yongbok Kim <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/helper.h
M target/mips/machine.c
M target/mips/op_helper.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Add CP0 PWSize register
Add PWSize register (CP0 Register 5, Select 7).
The PWSize register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
BDW (37..32) Base Directory index width (MIPS64 only)
GDW (29..24) Global Directory index width
UDW (23..18) Upper Directory index width
MDW (17..12) Middle Directory index width
PTW (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 103be64c26c166f12b3e1308edadef3443723ff1
https://github.com/qemu/qemu/commit/103be64c26c166f12b3e1308edadef3443723ff1
Author: Yongbok Kim <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/cpu.h
M target/mips/helper.h
M target/mips/machine.c
M target/mips/op_helper.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Add CP0 PWCtl register
Add PWCtl register (CP0 Register 5, Select 6).
The PWCtl register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
PWEn (31) - Hardware Page Table walker enable
PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only)
XK (28) - If 1, walker handles xkseg (MIPS64 only)
XS (27) - If 1, walker handles xsseg (MIPS64 only)
XU (26) - If 1, walker handles xuseg (MIPS64 only)
DPH (7) - Dual Page format of Huge Page support
HugePg (6) - Huge Page PTE supported in Directory levels
PSn (5..0) - Bit position of PTEvld in Huge Page PTE
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 630107955757b9dfc5c09f105caa267eded2e3b1
https://github.com/qemu/qemu/commit/630107955757b9dfc5c09f105caa267eded2e3b1
Author: Yongbok Kim <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add reset state for PWSize and PWField registers
Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 074cfcb4daedf59ccbbbc83c24eee80e0e8f4c71
https://github.com/qemu/qemu/commit/074cfcb4daedf59ccbbbc83c24eee80e0e8f4c71
Author: Yongbok Kim <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/helper.c
M target/mips/internal.h
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Implement hardware page table walker for MIPS32
Implement hardware page table walker. This implementation is
limiter only to MIPS32.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: fdac60cd0458f34b2e79d74a55bec10836e26471
https://github.com/qemu/qemu/commit/fdac60cd0458f34b2e79d74a55bec10836e26471
Author: Matthew Fortune <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>
Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions.
Their handling was permuted.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Matthew Fortune <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: d5ebcbaf09e8c14e62b2966446195be5eeabcbab
https://github.com/qemu/qemu/commit/d5ebcbaf09e8c14e62b2966446195be5eeabcbab
Author: Stefan Markovic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by
Coverity (CID 1395627).
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 0d30b3bbc5fed12da8f8d1bfd28f2803d65a4cb0
https://github.com/qemu/qemu/commit/0d30b3bbc5fed12da8f8d1bfd28f2803d65a4cb0
Author: Dimitrije Nikolic <address@hidden>
Date: 2018-10-18 (Thu, 18 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add opcodes for nanoMIPS EVA instructions
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Dimitrije Nikolic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 2ec24af2379e331d062a6fc1cda65bc262c7c17b
https://github.com/qemu/qemu/commit/2ec24af2379e331d062a6fc1cda65bc262c7c17b
Author: Peter Maydell <address@hidden>
Date: 2018-10-19 (Fri, 19 Oct 2018)
Changed paths:
M .mailmap
M include/elf.h
M linux-user/mips/target_syscall.h
M linux-user/mips64/target_syscall.h
M linux-user/syscall.c
M target/mips/cpu.h
M target/mips/helper.c
M target/mips/helper.h
M target/mips/internal.h
M target/mips/machine.c
M target/mips/mips-defs.h
M target/mips/op_helper.c
M target/mips/translate.c
M target/mips/translate_init.inc.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/amarkovic/tags/mips-queue-october-2018-part1-v2' into staging
MIPS queue October 2018, part1, v2
# gpg: Signature made Thu 18 Oct 2018 19:39:00 BST
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-october-2018-part1-v2: (28 commits)
target/mips: Add opcodes for nanoMIPS EVA instructions
target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH
target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>
target/mips: Implement hardware page table walker for MIPS32
target/mips: Add reset state for PWSize and PWField registers
target/mips: Add CP0 PWCtl register
target/mips: Add CP0 PWSize register
target/mips: Add CP0 PWField register
target/mips: Add CP0 PWBase register
target/mips: Add CP0 Config2 to DisasContext
target/mips: Improve DSP R2/R3-related naming
target/mips: Add availability control for DSP R3 ASE
target/mips: Add bit definitions for DSP R3 ASE
target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
target/mips: Increase 'supported ISAs/ASEs' flag holder size
target/mips: Add opcode values of MXU ASE
target/mips: Add organizational chart of MXU ASE
target/mips: Add assembler mnemonics list for MXU ASE
target/mips: Add basic description of MXU ASE
target/mips: Add a comment before each CP0 register section in cpu.h
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/77f7c7471936...2ec24af2379e
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