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[Qemu-commits] [qemu/qemu] fb23d6: hw/arm/virt: add DT property /secure-


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] fb23d6: hw/arm/virt: add DT property /secure-chosen/stdout...
Date: Tue, 16 Oct 2018 10:16:35 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fb23d693a3e0f22c25fdc2f373ac81d9cbb26680
      
https://github.com/qemu/qemu/commit/fb23d693a3e0f22c25fdc2f373ac81d9cbb26680
  Author: Jerome Forissier <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART

Bindings for /secure-chosen and /secure-chosen/stdout-path have been
proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2].
They've now been officially agreed on, so we can implement them
in QEMU.

This patch creates the property when the machine is secure.

[1] https://patchwork.kernel.org/patch/9602401/
[2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a

Signed-off-by: Jerome Forissier <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: commit message tweak]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9a05f7b67436abdc52bce899f56acfde2e831454
      
https://github.com/qemu/qemu/commit/9a05f7b67436abdc52bce899f56acfde2e831454
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Fix aarch64_sve_change_el wrt EL0

At present we assert:

  arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed.

The comment in arm_el_is_aa64 explains why asking about EL0 without
extra information is impossible.  Add an extra argument to provide
it from the surrounding context.

Fixes: 0ab5953b00b3
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a62e62af9f26bf655fe95ada796f28a6a16c0561
      
https://github.com/qemu/qemu/commit/a62e62af9f26bf655fe95ada796f28a6a16c0561
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Define fields of ISAR registers

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aaab8f3400ea5ec9c6cce3607ff26f9be89321d6
      
https://github.com/qemu/qemu/commit/aaab8f3400ea5ec9c6cce3607ff26f9be89321d6
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Align cortex-r5 id_isar0

The missing nibble made it more difficult to read.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37bdda89eb7615cb225f781c9fb552e144c68ea7
      
https://github.com/qemu/qemu/commit/37bdda89eb7615cb225f781c9fb552e144c68ea7
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Fix cortex-a7 id_isar0

The incorrect value advertised only thumb2 div without arm div.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b2d43091b59fc9937e68800b0ec3e76efd73690a
      
https://github.com/qemu/qemu/commit/b2d43091b59fc9937e68800b0ec3e76efd73690a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: Disable TSU feature bit

Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f02361822f73f28a4279783fdfb581c500660a36
      
https://github.com/qemu/qemu/commit/f02361822f73f28a4279783fdfb581c500660a36
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c
    M include/hw/net/cadence_gem.h

  Log Message:
  -----------
  net: cadence_gem: Use uint32_t for 32bit descriptor words

Use uint32_t instead of unsigned to describe 32bit descriptor words.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8568313f3bdf4bc1de7ace0eb5b92343fc19f3c8
      
https://github.com/qemu/qemu/commit/8568313f3bdf4bc1de7ace0eb5b92343fc19f3c8
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c
    M include/hw/net/cadence_gem.h

  Log Message:
  -----------
  net: cadence_gem: Add macro with max number of descriptor words

Add macro with max number of DMA descriptor words.
No functional change.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e48fdd9d90423d1530b49bbd61b4bbcb49198b33
      
https://github.com/qemu/qemu/commit/e48fdd9d90423d1530b49bbd61b4bbcb49198b33
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c
    M include/hw/net/cadence_gem.h

  Log Message:
  -----------
  net: cadence_gem: Add support for extended descriptors

Add support for extended descriptors with optional 64bit
addressing and timestamping. QEMU will not yet provide
timestamps (always leaving the valid timestamp bit as zero).

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 84aec8efd62052f6aeda570b328bc3ac484a1d30
      
https://github.com/qemu/qemu/commit/84aec8efd62052f6aeda570b328bc3ac484a1d30
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c
    M include/hw/net/cadence_gem.h

  Log Message:
  -----------
  net: cadence_gem: Add support for selecting the DMA MemoryRegion

Add support for selecting the Memory Region that the GEM
will do DMA to.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 357aa01335bbf715b7ad1ef621e4bc96e2ffbe19
      
https://github.com/qemu/qemu/commit/357aa01335bbf715b7ad1ef621e4bc96e2ffbe19
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: Implement support for 64bit descriptor addresses

Implement support for 64bit descriptor addresses.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 86278c33d1d71196f5e22ce3ce82a1b34a199754
      
https://github.com/qemu/qemu/commit/86278c33d1d71196f5e22ce3ce82a1b34a199754
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/arm-powerctl.c

  Log Message:
  -----------
  target-arm: powerctl: Enable HVC when starting CPUs to EL2

When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f11b452b95df4a0fc6561c278721cad03b24098b
      
https://github.com/qemu/qemu/commit/f11b452b95df4a0fc6561c278721cad03b24098b
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Add the Cortex-A72

Add the ARM Cortex-A72.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fc5f6856a02168864a5c1a46866a12839322222f
      
https://github.com/qemu/qemu/commit/fc5f6856a02168864a5c1a46866a12839322222f
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO

I previously fixed this for PMINTENSET_EL1, but missed these.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 599b71e277ac7e92807191b20b7163a28c5450ad
      
https://github.com/qemu/qemu/commit/599b71e277ac7e92807191b20b7163a28c5450ad
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mask PMOVSR writes based on supported counters

This is an amendment to my earlier patch:
    commit 7ece99b17e832065236c07a158dfac62619ef99b
    Author: Aaron Lindsay <address@hidden>
    Date:   Thu Apr 26 11:04:39 2018 +0100

        target/arm: Mask PMU register writes based on PMCR_EL0.N

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ab44c7b71fa683b9402bea0d367b87c881704188
      
https://github.com/qemu/qemu/commit/ab44c7b71fa683b9402bea0d367b87c881704188
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write

The get_phys_addr() functions take a pointer to an ARMMMUFaultInfo
struct, which they fill in only if a fault occurs. This means that
the caller must always zero-initialize the struct before passing
it in. We forgot to do this in v7m_stack_read() and v7m_stack_write().
Correct the error.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2ef297af07196c29446556537861f8e7dfeeae7b
      
https://github.com/qemu/qemu/commit/2ef297af07196c29446556537861f8e7dfeeae7b
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    A scripts/coccinelle/inplace-byteswaps.cocci

  Log Message:
  -----------
  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

Add a new Coccinelle script which replaces uses of the inplace
byteswapping functions *_to_cpus() and cpu_to_*s() with their
not-in-place equivalents. This is useful for where the swapping
is done on members of a packed struct -- taking the address
of the member to pass it to an inplace function is undefined
behaviour in C.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 09558375a634e17cea6cfbfec883ac2376d2dc7f
      
https://github.com/qemu/qemu/commit/09558375a634e17cea6cfbfec883ac2376d2dc7f
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M hw/arm/virt.c
    M hw/net/cadence_gem.c
    M include/hw/net/cadence_gem.h
    A scripts/coccinelle/inplace-byteswaps.cocci
    M target/arm/arm-powerctl.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging

target-arm queue:
 * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure 
UART
 * target/arm: Fix aarch64_sve_change_el wrt EL0
 * target/arm: Define fields of ISAR registers
 * target/arm: Align cortex-r5 id_isar0
 * target/arm: Fix cortex-a7 id_isar0
 * net/cadence_gem: Fix various bugs, add support for new
   features that will be used by the Xilinx Versal board
 * target-arm: powerctl: Enable HVC when starting CPUs to EL2
 * target/arm: Add the Cortex-A72
 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
 * target/arm: Mask PMOVSR writes based on supported counters
 * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
 * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

# gpg: Signature made Tue 16 Oct 2018 17:42:01 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181016-1:
  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
  target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  target/arm: Mask PMOVSR writes based on supported counters
  target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
  target/arm: Add the Cortex-A72
  target-arm: powerctl: Enable HVC when starting CPUs to EL2
  net: cadence_gem: Implement support for 64bit descriptor addresses
  net: cadence_gem: Add support for selecting the DMA MemoryRegion
  net: cadence_gem: Add support for extended descriptors
  net: cadence_gem: Add macro with max number of descriptor words
  net: cadence_gem: Use uint32_t for 32bit descriptor words
  net: cadence_gem: Disable TSU feature bit
  target/arm: Fix cortex-a7 id_isar0
  target/arm: Align cortex-r5 id_isar0
  target/arm: Define fields of ISAR registers
  target/arm: Fix aarch64_sve_change_el wrt EL0
  hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/dddb37495b84...09558375a634
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