[Qemu-commits] [qemu/qemu] a688e7: translate-all: fix locking of TBs whose two pages ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a688e73ba8c2e3b6f3e5e683c4a9c37d2ddc8984
      
https://github.com/qemu/qemu/commit/a688e73ba8c2e3b6f3e5e683c4a9c37d2ddc8984
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M accel/tcg/translate-all.c

  Log Message:
  -----------
  translate-all: fix locking of TBs whose two pages share the same physical page

Commit 0b5c91f ("translate-all: use per-page locking in !user-mode",
2018-06-15) introduced per-page locking. It assumed that the physical
pages corresponding to a TB (at most two pages) are always distinct,
which is wrong. For instance, an xtensa test provided by Max Filippov
is broken by the commit, since the test maps two virtual pages
to the same physical page:

        virt1: 7fff, virt2: 8000
        phys1 6000fff, phys2 6000000

Fix it by removing the assumption from page_lock_pair.
If the two physical page addresses are equal, we only lock
the PageDesc once. Note that the two callers of page_lock_pair,
namely page_unlock_tb and tb_link_page, are also updated so that
we do not try to unlock the same PageDesc twice.

Fixes: 0b5c91f74f3c83a36f37740969df8c775c997e69
Reported-by: Max Filippov <address@hidden>
Tested-by: Max Filippov <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 334692bce7f0653a93b8d84ecde8c847b08dec38
      
https://github.com/qemu/qemu/commit/334692bce7f0653a93b8d84ecde8c847b08dec38
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/softmmu_template.h
    M include/exec/cpu-all.h
    M include/exec/cpu_ldst.h

  Log Message:
  -----------
  tcg: Define and use new tlb_hit() and tlb_hit_page() functions

The condition to check whether an address has hit against a particular
TLB entry is not completely trivial. We do this in various places, and
in fact in one place (get_page_addr_code()) we have got the condition
wrong. Abstract it out into new tlb_hit() and tlb_hit_page() inline
functions (one for a known-page-aligned address and one for an
arbitrary address), and use them in all the places where we had the
condition correct.

This is a no-behaviour-change patch; we leave fixing the buggy
code in get_page_addr_code() to a subsequent patch.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e4c967a7201400d7f76e5847d5b4c4ac9e2566e0
      
https://github.com/qemu/qemu/commit/e4c967a7201400d7f76e5847d5b4c4ac9e2566e0
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()

In commit 71b9a45330fe220d1 we changed the condition we use
to determine whether we need to refill the TLB in
get_page_addr_code() to
    if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=
           (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) {

This isn't the right check (it will falsely fail if the
input addr happens to have the low bit corresponding to
TLB_INVALID_MASK set, for instance). Replace it with a
use of the new tlb_hit() function, which is the correct test.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 4b1a3e1e34ad971b58783d4a24448ccbf5bd8fd4
      
https://github.com/qemu/qemu/commit/4b1a3e1e34ad971b58783d4a24448ccbf5bd8fd4
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Don't treat invalid TLB entries as needing recheck

In get_page_addr_code() when we check whether the TLB entry
is marked as TLB_RECHECK, we should not go down that code
path if the TLB entry is not valid at all (ie the TLB_INVALID
bit is set).

Tested-by: Laurent Vivier <address@hidden>
Reported-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 68fea038553039e53d425c6399202d13f1e5cfb8
      
https://github.com/qemu/qemu/commit/68fea038553039e53d425c6399202d13f1e5cfb8
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Avoid caching overwritten tlb entries

When installing a TLB entry, remove any cached version of the
same page in the VTLB.  If the existing TLB entry matches, do
not copy into the VTLB, but overwrite it.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9c8c334b0637bf3c592d432b0c11f3b62dd5dba3
      
https://github.com/qemu/qemu/commit/9c8c334b0637bf3c592d432b0c11f3b62dd5dba3
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M include/qom/cpu.h

  Log Message:
  -----------
  cpu: Assert asidx_from_attrs return value in range

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ab08440a4ee09032d1a9cb22fdcab23bc7e1c656
      
https://github.com/qemu/qemu/commit/ab08440a4ee09032d1a9cb22fdcab23bc7e1c656
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/softmmu_template.h
    M accel/tcg/translate-all.c
    M include/exec/cpu-all.h
    M include/exec/cpu_ldst.h
    M include/qom/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180702' into staging

Assorted tlb and tb caching fixes

# gpg: Signature made Mon 02 Jul 2018 17:03:07 BST
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20180702:
  cpu: Assert asidx_from_attrs return value in range
  accel/tcg: Avoid caching overwritten tlb entries
  accel/tcg: Don't treat invalid TLB entries as needing recheck
  accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()
  tcg: Define and use new tlb_hit() and tlb_hit_page() functions
  translate-all: fix locking of TBs whose two pages share the same physical page

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e14dcc9cda98...ab08440a4ee0
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