[Qemu-commits] [qemu/qemu] 14ec3c: device_tree: Increase FDT_MAX_SIZE to 1 MiB

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 14ec3cbd7c1e31dca4d23f028100c8f43e156573
      
https://github.com/qemu/qemu/commit/14ec3cbd7c1e31dca4d23f028100c8f43e156573
  Author: Geert Uytterhoeven <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M device_tree.c

  Log Message:
  -----------
  device_tree: Increase FDT_MAX_SIZE to 1 MiB

It is not uncommon for a contemporary FDT to be larger than 64 KiB,
leading to failures loading the device tree from sysfs:

    qemu-system-aarch64: qemu_fdt_setprop: Couldn't set ...: FDT_ERR_NOSPACE

Hence increase the limit to 1 MiB, like on PPC.

For reference, the largest arm64 DTB created from the Linux sources is
ca. 75 KiB large (100 KiB when built with symbols/fixup support).

Cc: address@hidden
Signed-off-by: Geert Uytterhoeven <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 75ed2c02484101d5b4995c56e78a894ac244ce05
      
https://github.com/qemu/qemu/commit/75ed2c02484101d5b4995c56e78a894ac244ce05
  Author: Igor Mammedov <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  arm: always start from first_cpu when registering loader cpu reset callback

if arm_load_kernel() were passed non first_cpu, QEMU would end up
with partially set do_cpu_reset() callback leaving some CPUs without it.

Make sure that do_cpu_reset() is registered for all CPUs by enumerating
CPUs from first_cpu.

(In practice every board that we have was passing us the first CPU
as the boot CPU, either directly or indirectly, so this wasn't
causing incorrect behaviour.)

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added a note that this isn't a behaviour change]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 145772707fe80395b87c244ccf5699a756f1946b
      
https://github.com/qemu/qemu/commit/145772707fe80395b87c244ccf5699a756f1946b
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove stale TODO comment

Remove a stale TODO comment -- we have now made the arm_ldl_ptw()
and arm_ldq_ptw() functions propagate physical memory read errors
out to their callers.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 4818bad98c8212fbbb0525d10761b6b65279ab92
      
https://github.com/qemu/qemu/commit/4818bad98c8212fbbb0525d10761b6b65279ab92
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Use v7m_stack_read() for reading the frame signature

In commit 95695effe8caa552b8f2 we changed the v7M/v8M stack
pop code to use a new v7m_stack_read() function that checks
whether the read should fail due to an MPU or bus abort.
We missed one call though, the one which reads the signature
word for the callee-saved register part of the frame.

Correct the omission.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ccbc0e338486b21cb0eb52e52cd309bbbe6a7507
      
https://github.com/qemu/qemu/commit/ccbc0e338486b21cb0eb52e52cd309bbbe6a7507
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Check PMCNTEN for whether PMCCNTR is enabled

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 169c893874977eee8303a6dad4a3f25c5464858f
      
https://github.com/qemu/qemu/commit/169c893874977eee8303a6dad4a3f25c5464858f
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0

They share the same underlying state

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7ece99b17e832065236c07a158dfac62619ef99b
      
https://github.com/qemu/qemu/commit/7ece99b17e832065236c07a158dfac62619ef99b
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mask PMU register writes based on PMCR_EL0.N

This is in preparation for enabling counters other than PMCCNTR

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d5a5e4c93dae0dc3feb402cf7ee78d846da1a7e1
      
https://github.com/qemu/qemu/commit/d5a5e4c93dae0dc3feb402cf7ee78d846da1a7e1
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Fetch GICv3 state directly from CPUARMState

This eliminates the need for fetching it from el_change_hook_opaque, and
allows for supporting multiple el_change_hooks without having to hack
something together to find the registered opaque belonging to GICv3.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 08267487c99e8150382420936ab72c1e0ad74ce3
      
https://github.com/qemu/qemu/commit/08267487c99e8150382420936ab72c1e0ad74ce3
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Support multiple EL change hooks

Signed-off-by: Aaron Lindsay <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b5c53d1b3886387874f8c8582b205aeb3e4c3df6
      
https://github.com/qemu/qemu/commit/b5c53d1b3886387874f8c8582b205aeb3e4c3df6
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Add pre-EL change hooks

Because the design of the PMU requires that the counter values be
converted between their delta and guest-visible forms for mode
filtering, an additional hook which occurs before the EL is changed is
necessary.

Signed-off-by: Aaron Lindsay <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e69ad9df6c2fe98713e5391a9161da9c6d7a9f22
      
https://github.com/qemu/qemu/commit/e69ad9df6c2fe98713e5391a9161da9c6d7a9f22
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Allow EL change hooks to do IO

During code generation, surround CPSR writes and exception returns which
call the EL change hooks with gen_io_start/end. The immediate need is
for the PMU to access the clock and icount during EL change to support
mode filtering.

Signed-off-by: Aaron Lindsay <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ac57fd24cd864d42e7551f82266bc0930bd39547
      
https://github.com/qemu/qemu/commit/ac57fd24cd864d42e7551f82266bc0930bd39547
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix bitmask for PMCCFILTR writes

It was shifted to the left one bit too few.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e4e91a217c17fff4045dd4b423cdcb471b3d6a0e
      
https://github.com/qemu/qemu/commit/e4e91a217c17fff4045dd4b423cdcb471b3d6a0e
  Author: Aaron Lindsay <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide

This is a bug fix to ensure 64-bit reads of these registers don't read
adjacent data.

Signed-off-by: Aaron Lindsay <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b901a172455cfbb96cc36e916ebc65f0bfed8109
      
https://github.com/qemu/qemu/commit/b901a172455cfbb96cc36e916ebc65f0bfed8109
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Don't bother setting default_cpu_type

In commit 210f47840dd62, we changed the bcm2836 SoC object to
always create a CPU of the correct type for that SoC model. This
makes the default_cpu_type settings in the MachineClass structs
for the raspi2 and raspi3 boards redundant. We didn't change
those at the time because it would have meant a temporary
regression in a corner case of error handling if the user
requested a non-existing CPU type. The -cpu parse handling
changes in 2278b93941d42c3 mean that it no longer implicitly
depends on default_cpu_type for this to work, so we can now
delete the redundant default_cpu_type fields.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: eb7d1f176381466660a730f14eff3d521686aa31
      
https://github.com/qemu/qemu/commit/eb7d1f176381466660a730f14eff3d521686aa31
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  hw/arm/highbank: don't make sysram 'nomigrate'

Currently we use memory_region_init_ram_nomigrate() to create
the "highbank.sysram" memory region, and we don't manually
register it with vmstate_register_ram(). This currently
means that its contents are migrated but as a ram block
whose name is the empty string; in future it may mean they
are not migrated at all. Use memory_region_init_ram() instead.

Note that this is a cross-version migration compatibility
break for the "highbank" and "midway" machines.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 44cf837d38c3af178711781ffdc61776763e40d1
      
https://github.com/qemu/qemu/commit/44cf837d38c3af178711781ffdc61776763e40d1
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'

Currently we use memory_region_init_ram_nomigrate() to create
the "aspeed.boot_rom" memory region, and we don't manually
register it with vmstate_register_ram(). This currently
means that its contents are migrated but as a ram block
whose name is the empty string; in future it may mean they
are not migrated at all. Use memory_region_init_ram() instead.

Note that would be a cross-version migration compatibility break
for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines,
but migration is currently broken for them.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden


  Commit: a2e9989c96aaa0e0d993e7b44eb6c2da2f9214ac
      
https://github.com/qemu/qemu/commit/a2e9989c96aaa0e0d993e7b44eb6c2da2f9214ac
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM

Currently we use vmstate_register_ram_global() for the SRAM;
this is not a good idea for devices, because it means that
you can only ever create one instance of the device, as
the second instance would get a RAM block name clash.
Instead, use memory_region_init_ram(), which automatically
registers the RAM block with a local-to-the-device name.

Note that this would be a cross-version migration compatibility break
for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines,
but migration is currently broken for them.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden


  Commit: 6b892b2f79796989c78d6977e4c906448cda69c0
      
https://github.com/qemu/qemu/commit/6b892b2f79796989c78d6977e4c906448cda69c0
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/timer/aspeed_timer.c

  Log Message:
  -----------
  timer/aspeed: fix vmstate version id

commit 1d3e65aa7ac5 ("hw/timer: Add value matching support to
aspeed_timer") increased the vmstate version of aspeed.timer because
the state had changed, but it also bumped the version of the
VMSTATE_STRUCT_ARRAY under the aspeed.timerctrl which did not need to.

Change back this version to fix migration.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fbf32752663878947de455ff57cb5b9318f14bec
      
https://github.com/qemu/qemu/commit/fbf32752663878947de455ff57cb5b9318f14bec
  Author: Sai Pavan Boddu <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo

SNOOP_NONE state handle is moved above in the if ladder, as it's same
as SNOOP_STRIPPING during data cycles.

Signed-off-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 20b2323edf8d42fe024902ca7d847b9f71c98df1
      
https://github.com/qemu/qemu/commit/20b2323edf8d42fe024902ca7d847b9f71c98df1
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-26 (Thu, 26 Apr 2018)

  Changed paths:
    M device_tree.c
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/arm/boot.c
    M hw/arm/highbank.c
    M hw/arm/raspi.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/ssi/xilinx_spips.c
    M hw/timer/aspeed_timer.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180426' 
into staging

target-arm queue:
 * xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
 * timer/aspeed: fix vmstate version id
 * hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
 * hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
 * hw/arm/highbank: don't make sysram 'nomigrate'
 * hw/arm/raspi: Don't bother setting default_cpu_type
 * PMU emulation: some minor bugfixes and preparation for
   support of other events than just the cycle counter
 * target/arm: Use v7m_stack_read() for reading the frame signature
 * target/arm: Remove stale TODO comment
 * arm: always start from first_cpu when registering loader cpu reset callback
 * device_tree: Increase FDT_MAX_SIZE to 1 MiB

# gpg: Signature made Thu 26 Apr 2018 11:46:31 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180426:
  xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo
  timer/aspeed: fix vmstate version id
  hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM
  hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'
  hw/arm/highbank: don't make sysram 'nomigrate'
  hw/arm/raspi: Don't bother setting default_cpu_type
  target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide
  target/arm: Fix bitmask for PMCCFILTR writes
  target/arm: Allow EL change hooks to do IO
  target/arm: Add pre-EL change hooks
  target/arm: Support multiple EL change hooks
  target/arm: Fetch GICv3 state directly from CPUARMState
  target/arm: Mask PMU register writes based on PMCR_EL0.N
  target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0
  target/arm: Check PMCNTEN for whether PMCCNTR is enabled
  target/arm: Use v7m_stack_read() for reading the frame signature
  target/arm: Remove stale TODO comment
  arm: always start from first_cpu when registering loader cpu reset callback
  device_tree: Increase FDT_MAX_SIZE to 1 MiB

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/569df5b6e118...20b2323edf8d