[Qemu-commits] [qemu/qemu] 7ea6e0: ppc/xics: register reset handlers for the ICP and ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 7ea6e0671754330510bcdde2e7f5b5f2db426472
      
https://github.com/qemu/qemu/commit/7ea6e0671754330510bcdde2e7f5b5f2db426472
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-03-06 (Mon, 06 Mar 2017)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/ppc/spapr.c

  Log Message:
  -----------
  ppc/xics: register reset handlers for the ICP and ICS objects

The recent changes on the XICS layer removed the XICSState object to
let the sPAPR machine handle the ICP and ICS directly. The reset of
these objects was previously handled by XICSState, which was a SysBus
device, and to keep the same behavior, the ICP and ICS were assigned
to SysbBus.

But that broke the 'info qtree' command in the monitor. 'qtree'
performs a loop on the children of a bus to print their properties and
SysBus devices are expected to be found under SysBus, which is not the
case anymore.

The fix for this problem is to register reset handlers for the ICP and
ICS objects and stop using SysBus for such devices.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Tested-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 17b7c39e275ecacae1416bc164189d6ddd116c57
      
https://github.com/qemu/qemu/commit/17b7c39e275ecacae1416bc164189d6ddd116c57
  Author: Igor Mammedov <address@hidden>
  Date:   2017-03-06 (Mon, 06 Mar 2017)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: ensure that all threads within core are on the same NUMA node

Threads within a core shouldn't be on different
NUMA nodes, so if user has misconfgured command
line, fail QEMU at start up to force user fix it.

For now use the first thread on the core as source
of core's node-id. Later when cpu-numa refactoring
lands  it will be switched to core's node-id from
possible_cpus[].

This prevents the same problems as commit 20bb648d
"spapr: Fix default NUMA node allocation for threads",
but for the case of manually configured NUMA node
mappings, instead of just the default case.

Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 806c9d71abbcd283c0a6d8250e5a6db951ba9494
      
https://github.com/qemu/qemu/commit/806c9d71abbcd283c0a6d8250e5a6db951ba9494
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2017-03-06 (Mon, 06 Mar 2017)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: fmadd check for excp independently

Current order of checking does not confirm with the spec
(ISA 3.0: MultiplyAddDP page-469). Change the order and make them
independent of each other.

For example: a = infinity, b = zero, c = SNaN, this should set both
VXIMZ and VXNAN

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3e5b26cf57a28c2e33655205d8f49e633a75fa8c
      
https://github.com/qemu/qemu/commit/3e5b26cf57a28c2e33655205d8f49e633a75fa8c
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2017-03-06 (Mon, 06 Mar 2017)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: fmadd: add macro for updating flags

Adds FPU_MADDSUB_UPDATE macro, this will be used for other routines
having float32/16

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 182fe2cf19e829e34f63443ee1ccd9f799715c2c
      
https://github.com/qemu/qemu/commit/182fe2cf19e829e34f63443ee1ccd9f799715c2c
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2017-03-06 (Mon, 06 Mar 2017)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: use helper for excp handling

Use the helper routine float[32,64]_maddsub_update_excp() in VSX_MADD
macro.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 56b51708e9e22809d2a78f38d0ac84bb3f3fca92
      
https://github.com/qemu/qemu/commit/56b51708e9e22809d2a78f38d0ac84bb3f3fca92
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-06 (Mon, 06 Mar 2017)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170306' into 
staging

ppc patch queue for 2017-03-06

Looks like my previous batch wasn't quite the last before hard freeze.
This has a handful of bugfixes to go in.  They're all genuine
bugfixes, though not regressions in some cases.

# gpg: Signature made Mon 06 Mar 2017 04:07:48 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.9-20170306:
  target/ppc: use helper for excp handling
  target/ppc: fmadd: add macro for updating flags
  target/ppc: fmadd check for excp independently
  spapr: ensure that all threads within core are on the same NUMA node
  ppc/xics: register reset handlers for the ICP and ICS objects

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/fbddc2e5608e...56b51708e9e2