[Qemu-commits] [qemu/qemu] 9b44c8: target/ppc: Add POWER9/ISAv3.00 to compat_table

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9b44c836dc37507513eb67cea862f82dafa249d8
      
https://github.com/qemu/qemu/commit/9b44c836dc37507513eb67cea862f82dafa249d8
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/compat.c

  Log Message:
  -----------
  target/ppc: Add POWER9/ISAv3.00 to compat_table

compat_table contains the list of logical pvr compat modes which a cpu can
operate in. It is a list of struct CompatInfo which contains the given pvr
value for a compat mode, the pcr bits which should be set to operate in
that compat mode, the pcr level which must be present in pcr_supported for
a processor to support that compat mode and the max threads possible in
that compat mode.

Add an entry for the POWER9/ISAv3.00 logical pvr which represents a
processor running with support for logical pvr 0x0f000005. A processor
running in this mode should have PCR_COMPAT_3_00 set in the pcr (if
available in pcr_mask) and should have PCR_COMPAT_3_00 in pcr_supported
to indicate that it is capable of running in this compat mode.

Also add PCR_COMPAT_3_00 to the bits which must be set for all previous
compat modes. Since no processor models contain this bit yet in pcr_mask
it will never be set, but this ensures we don't forget to in the future.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9c60766887c647df7193463f7a2075e8993b514c
      
https://github.com/qemu/qemu/commit/9c60766887c647df7193463f7a2075e8993b514c
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M exec.c
    M include/exec/ram_addr.h
    M include/qemu/mmap-alloc.h
    M target/ppc/kvm.c
    M util/mmap-alloc.c

  Log Message:
  -----------
  exec, kvm, target-ppc: Move getrampagesize() to common code

getrampagesize() returns the largest supported page size and mainly
used to know if huge pages are enabled.

However is implemented in target-ppc/kvm.c and not available
in TCG or other architectures.

This renames and moves gethugepagesize() to mmap-alloc.c where
fd-based analog of it is already implemented. This renames and moves
getrampagesize() to exec.c as it seems to be the common place for
helpers like this.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eaa477ca4ef59eed2c77d81937b981ff823def3b
      
https://github.com/qemu/qemu/commit/eaa477ca4ef59eed2c77d81937b981ff823def3b
  Author: David Gibson <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M tests/boot-serial-test.c
    M tests/pnv-xscom-test.c

  Log Message:
  -----------
  powernv: Don't test POWER9 CPU yet

A couple of tests for the work-in-progress 'powernv' machine type attempt
to test on POWER9 CPUs.  However the POWER9 CPU support is incomplete and
this doesn't really work.  In particular the firmware image we have
currently assumes the presence of the SDR1 register, which no longer exists
on POWER9.  We only got away with this so far, because of a different bug
which added SDR1 to POWER9 even though it shouldn't be there.

For now, remove POWER9 testing of powernv, POWER8 testing will do for now
until the POWER9 support is more complete.

Signed-off-by: David Gibson <address@hidden>


  Commit: 0922f1e4872656f7643fb2bc8459bea6964de085
      
https://github.com/qemu/qemu/commit/0922f1e4872656f7643fb2bc8459bea6964de085
  Author: David Gibson <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/cpu-qom.h

  Log Message:
  -----------
  target/ppc/POWER9: Add POWERPC_MMU_V3 bit

For easier handling of future processors using the POWER9 or something
close to it, add a new bit in the MMU model.  This was originally from a
revised version of 86cf1e9 "target/ppc/POWER9: Add ISAv3.00 MMU definition"
but the older version of the patch was already merged.  This makes the
change on top of the original version.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9861bb3efd2a4def622cd40afb58af61542c4458
      
https://github.com/qemu/qemu/commit/9861bb3efd2a4def622cd40afb58af61542c4458
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/ppc/spapr.h
    M target/ppc/cpu.h

  Log Message:
  -----------
  target/ppc: Add patb_entry to sPAPRMachineState

ISA v3.00 adds the idea of a partition table which is used to store the
address translation details for all partitions on the system. The partition
table consists of double word entries indexed by partition id where the second
double word contains the location of the process table in guest memory. The
process table is registered by the guest via a h-call.

We need somewhere to store the address of the process table so we add an entry
to the sPAPRMachineState struct called patb_entry to represent the second
doubleword of a single partition table entry corresponding to the current
guest. We need to store this value so we know if the guest is using radix or
hash translation and the location of the corresponding process table in guest
memory. Since we only have a single guest per qemu instance, we only need one
entry.

Since the partition table is technically a hypervisor resource we require that
access to it is abstracted by the virtual hypervisor through the get_patbe()
call. Currently the value of the entry is never set (and thus
defaults to 0 indicating hash), but it will be required to both implement
POWER9 kvm support and tcg radix support.

We also add this field to be migrated as part of the sPAPRMachineState as we
will need it on the receiving side as the guest will never tell us this
information again and we need it to perform translation.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f4f28ffc1decf842b194644510e0d7f646af4c1
      
https://github.com/qemu/qemu/commit/4f4f28ffc1decf842b194644510e0d7f646af4c1
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/translate.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Don't gen an SDR1 on POWER9 and rework register creation

POWER9 doesn't have a storage description register 1 (SDR1) which is used
to store the base and size of the hash table. Thus we don't need to
generate this register on the POWER9 cpu model. While we're here, the
register generation code for 970, POWER5+, POWER<7/8/9> in general is a
mess where we call a generic function from a model specific function which
then attempts to call model specific functions, so rework this for
readability.

We update ppc_cpu_dump_state so that "info registers" will only display
the value of sdr1 if the register has been generated.

As mentioned above the register generation for the pcc->init_proc
function for 970, POWER5+, POWER7, POWER8 and POWER9 has been reworked
for improved clarity. Instead of calling init_proc_book3s_64 which then
attempts to generate the correct registers through a mess of if statements,
we remove this function and instead call the appropriate register
generation functions directly. This follows the register generation model
used for earlier cpu models (pre-970) whereby cpu specific registers are
generated directly in the init_proc function and makes it easier to
add/remove specific registers for new cpu models.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b2899495e3bd467adb9ef195655407cd58a97ded
      
https://github.com/qemu/qemu/commit/b2899495e3bd467adb9ef195655407cd58a97ded
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/Makefile.objs
    A target/ppc/mmu-book3s-v3.c
    A target/ppc/mmu-book3s-v3.h
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu_helper.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc/POWER9: Add POWER9 mmu fault handler

Add a new mmu fault handler for the POWER9 cpu and add it as the handler
for the POWER9 cpu definition.

This handler checks if the guest is radix or hash based on the value in the
partition table entry and calls the correct fault handler accordingly.

The hash fault handling code has also been updated to check if the
partition is using segment tables.

Currently only legacy hash (no segment tables) is supported.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4975c098c9f4f96d433e88ab1b63d0d7e2a48ce0
      
https://github.com/qemu/qemu/commit/4975c098c9f4f96d433e88ab1b63d0d7e2a48ce0
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  target/ppc/POWER9: Add POWER9 pa-features definition

Add a pa-features definition which includes all of the new fields which
have been added, note we don't claim support for any of these new features
at this stage.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Balbir Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6f46dcb3e5b9352ad3479bd6f005576510ee45fb
      
https://github.com/qemu/qemu/commit/6f46dcb3e5b9352ad3479bd6f005576510ee45fb
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc/POWER9: Add cpu_has_work function for POWER9

The cpu has work function is used to mask interrupts used to determine
if there is work for the cpu based on the LPCR. Add a function to do this
for POWER9 and add it to the POWER9 cpu definition. This is similar to that
for POWER8 except using the LPCR bits as defined for POWER9.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 24d8e5655f3da3f07cbb8689419ca9836c70fa94
      
https://github.com/qemu/qemu/commit/24d8e5655f3da3f07cbb8689419ca9836c70fa94
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  hw/ppc/spapr: Add POWER9 to pseries cpu models

Add POWER9 cpu to list of spapr core models which allows it to be specified
as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9).

This now allows a POWER9 cpu to boot to userspace in tcg emulation for a
pseries machine with a legacy kernel.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Balbir Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a6152b52bc50c5cf1cd118a74b483dd3f0748ebd
      
https://github.com/qemu/qemu/commit/a6152b52bc50c5cf1cd118a74b483dd3f0748ebd
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/mmu-hash64.c

  Log Message:
  -----------
  target/ppc: Add Instruction Authority Mask Register Check

The instruction authority mask register (IAMR) can be used to restrict
permissions for instruction fetch accesses on a per key basis for each
of 32 different key values. Access permissions are derived based on the
specific key value stored in the relevant page table entry.

The IAMR was introduced in, and is present in processors since, POWER8
(ISA v2.07). Thus introduce a function to check access permissions based
on the pte key value and the contents of the IAMR when handling a page
fault to ensure sufficient access permissions for an instruction fetch.

A hash pte contains a key value in bits 2:3|52:54 of the second double word
of the pte, this key value gives an index into the IAMR which contains 32
2-bit access masks. If the least significant bit of the 2-bit access mask
corresponding to the given key value is set (IAMR[key] & 0x1 == 0x1) then
the instruction fetch is not permitted and an ISI is generated accordingly.
While we're here, add defines for the srr1 bits to be set for the ISI for
clarity.

e.g.

pte:
dw0 [XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]
dw1 [XX01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX010XXXXXXXXX]
       ^^                                                ^^^
key = 01010 (0x0a)

IAMR: [XXXXXXXXXXXXXXXXXXXX01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]
                     ^^
Access mask = 0b01

Test access mask: 0b01 & 0x1 == 0x1

Least significant bit of the access mask is set, thus the instruction fetch
is not permitted. We should generate an instruction storage interrupt (ISI)
with bit 42 of SRR1 set to indicate access precluded by virtual page class
key protection.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
[dwg: Move new constants to cpu.h, since they're not MMUv3 specific]
Signed-off-by: David Gibson <address@hidden>


  Commit: 347a5c73bafd1b5872c9d3192a4d08f8aa1d5f5a
      
https://github.com/qemu/qemu/commit/347a5c73bafd1b5872c9d3192a4d08f8aa1d5f5a
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/mmu-hash64.c

  Log Message:
  -----------
  target/ppc: Add execute permission checking to access authority check

Basic storage protection defines various access authority permissions
based on a slb storage key and pte pp value pair. This access authority
defines read, write and execute permissions however currently we only
use this to control read and write permissions and ignore the execute
control.

Fix the code to allow execute permissions based on the key-pp value pair.
Execute is allowed under the same conditions which enable reads.
(i.e. read permission -> execute permission)

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Acked-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 07a68f990785a8574c78a36b21cf5165e46f1113
      
https://github.com/qemu/qemu/commit/07a68f990785a8574c78a36b21cf5165e46f1113
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/mmu-hash64.c

  Log Message:
  -----------
  target/ppc: Move no-execute and guarded page checking into new function

A pte entry has bit fields which can be used to make a page no-execute or
guarded, if either of these bits are set then an instruction access to this
page will fail. Currently these bits are checked with the pp_prot function
however the ISA specifies that the access authority controlled by the
key-pp value pair should only be checked on an instruction access after
the no-execute and guard bits have already been verified to permit the
access.

Move the no-execute and guard bit checking into a new separate function.
Note that we can remove the check for the no-execute bit in the slb entry
since this check was already performed above when we obtained the slb
entry.

In the event that the no-execute or guard bits are set, an ISI should be
generated with the SRR1_NOEXEC_GUARD (0x10000000) bit set in srr1. Add a
define for this for clarity.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
[dwg: Move constants to cpu.h since they're not MMUv3 specific]
Signed-off-by: David Gibson <address@hidden>


  Commit: da82c73a950a99b9d6c1ec3eba3d1d6034effd43
      
https://github.com/qemu/qemu/commit/da82c73a950a99b9d6c1ec3eba3d1d6034effd43
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/mmu-hash64.c

  Log Message:
  -----------
  target/ppc: Rework hash mmu page fault code and add defines for clarity

The hash mmu page fault handling code is responsible for generating ISIs
and DSIs when access permissions cause an access to fail. Part of this
involves setting the srr1 or dsisr registers to indicate what causes the
access to fail. Add defines for the bit fields of these registers and
rework the code to use these new defines in order to improve readability
and code clarity.

While we're here, update what is logged when an access fails to include
information as to what caused to access to fail for debug purposes.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
[dwg: Moved constants to cpu.h since they're not MMUv3 specific]
Signed-off-by: David Gibson <address@hidden>


  Commit: bb998645284924db6da93e777af5f29ef2f3c0a8
      
https://github.com/qemu/qemu/commit/bb998645284924db6da93e777af5f29ef2f3c0a8
  Author: David Gibson <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Advertise access to PCIe extended config space

The (paravirtual) PCI host bridge on the 'pseries' machine in most
regards acts like a regular PCI bus, rather than a PCIe bus.  Despite
this, though, it does allow access to the PCIe extended config space.

We already implemented the RTAS methods to allow this access.. but
forgot to put the markers into the device tree so that guest's know it
is there.  This adds them in.

With this, a pseries guest is able to view extended config space on
(for example an e1000e device.  This should be enough to allow guests
to use at least some PCIe devices.

Signed-off-by: David Gibson <address@hidden>


  Commit: ec975e839cbb6143be80cfc91b1df103fc7e4771
      
https://github.com/qemu/qemu/commit/ec975e839cbb6143be80cfc91b1df103fc7e4771
  Author: Sam Bobroff <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M hw/ppc/spapr.c
    M target/ppc/cpu-qom.h
    M target/ppc/kvm.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu_helper.c
    M target/ppc/translate.c

  Log Message:
  -----------
  spapr: Small cleanup of PPC MMU enums

The PPC MMU types are sometimes treated as if they were a bit field
and sometime as if they were an enum which causes maintenance
problems: flipping bits in the MMU type (which is done on both the 1TB
segment and 64K segment bits) currently produces new MMU type
values that are not handled in every "switch" on it, sometimes causing
an abort().

This patch provides some macros that can be used to filter out the
"bit field-like" bits so that the remainder of the value can be
switched on, like an enum. This allows removal of all of the
"degraded" types from the list and should ease maintenance.

Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 992d7e976c7eca2b3129cd4bae4a0d350a8065fa
      
https://github.com/qemu/qemu/commit/992d7e976c7eca2b3129cd4bae4a0d350a8065fa
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2017-03-03 (Fri, 03 Mar 2017)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: rewrite f[n]m[add,sub] using float64_muladd

Use the softfloat api for fused multiply-add.
Introduce routine to set the FPSCR flags VXNAN, VXIMZ nad VMISI.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 17783ac828adc694d986698d2d7014aedfeb48c6
      
https://github.com/qemu/qemu/commit/17783ac828adc694d986698d2d7014aedfeb48c6
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-04 (Sat, 04 Mar 2017)

  Changed paths:
    M exec.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_pci.c
    M include/exec/ram_addr.h
    M include/hw/ppc/spapr.h
    M include/qemu/mmap-alloc.h
    M target/ppc/Makefile.objs
    M target/ppc/compat.c
    M target/ppc/cpu-qom.h
    M target/ppc/cpu.h
    M target/ppc/fpu_helper.c
    M target/ppc/kvm.c
    A target/ppc/mmu-book3s-v3.c
    A target/ppc/mmu-book3s-v3.h
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu_helper.c
    M target/ppc/translate.c
    M target/ppc/translate_init.c
    M tests/boot-serial-test.c
    M tests/pnv-xscom-test.c
    M util/mmap-alloc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170303' into 
staging

ppc patch queuye for 2017-03-03

This will probably be my last pull request before the hard freeze.  It
has some new work, but that has all been posted in draft before the
soft freeze, so I think it's reasonable to include in qemu-2.9.

This batch has:
    * A substantial amount of POWER9 work
  * Implements the legacy (hash) MMU for POWER9
        * Some more preliminaries for implementing the POWER9 radix
    MMU
        * POWER9 has_work
        * Basic POWER9 compatibility mode handling
        * Removal of some premature tests
    * Some cleanups and fixes to the existing MMU code to make the
      POWER9 work simpler
    * A bugfix for TCG multiply adds on power
    * Allow pseries guests to access PCIe extended config space

This also includes a code-motion not strictly in ppc code - moving
getrampagesize() from ppc code to exec.c.  This will make some future
VFIO improvements easier, Paolo said it was ok to merge via my tree.

# gpg: Signature made Fri 03 Mar 2017 03:20:36 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.9-20170303:
  target/ppc: rewrite f[n]m[add,sub] using float64_muladd
  spapr: Small cleanup of PPC MMU enums
  spapr_pci: Advertise access to PCIe extended config space
  target/ppc: Rework hash mmu page fault code and add defines for clarity
  target/ppc: Move no-execute and guarded page checking into new function
  target/ppc: Add execute permission checking to access authority check
  target/ppc: Add Instruction Authority Mask Register Check
  hw/ppc/spapr: Add POWER9 to pseries cpu models
  target/ppc/POWER9: Add cpu_has_work function for POWER9
  target/ppc/POWER9: Add POWER9 pa-features definition
  target/ppc/POWER9: Add POWER9 mmu fault handler
  target/ppc: Don't gen an SDR1 on POWER9 and rework register creation
  target/ppc: Add patb_entry to sPAPRMachineState
  target/ppc/POWER9: Add POWERPC_MMU_V3 bit
  powernv: Don't test POWER9 CPU yet
  exec, kvm, target-ppc: Move getrampagesize() to common code
  target/ppc: Add POWER9/ISAv3.00 to compat_table

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/eeb61d4f8270...17783ac828ad