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[Qemu-commits] [qemu/qemu] 196fe2: spapr_vscsi: fix build error introduc
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Subject: |
[Qemu-commits] [qemu/qemu] 196fe2: spapr_vscsi: fix build error introduced by f19661c... |
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Date: |
Thu, 06 Oct 2016 07:00:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 196fe23734ca8888ca0275ad203ccb0d20907e6d
https://github.com/qemu/qemu/commit/196fe23734ca8888ca0275ad203ccb0d20907e6d
Author: Felipe Franciosi <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M hw/scsi/spapr_vscsi.c
M hw/scsi/trace-events
Log Message:
-----------
spapr_vscsi: fix build error introduced by f19661c8
A typo introduced in f19661c8 prevents qemu from building when configured
with --enable-trace-backend=dtrace.
Signed-off-by: Felipe Franciosi <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1485ef1c45eb349c841c22b1d31a51a5ece68a89
https://github.com/qemu/qemu/commit/1485ef1c45eb349c841c22b1d31a51a5ece68a89
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M tests/Makefile.include
M tests/boot-sector.c
M tests/pxe-test.c
Log Message:
-----------
tests: Test IPv6 and ppc64 in the PXE tester
The firmware of the pseries machine, SLOF, is able to load files via
IPv6 networking, too. So to test both, network bootloading on ppc64
and IPv6 (via Slirp) , let's add some PXE tests for this environment,
too. Since we can not use the normal x86 boot sector for network boot
loading, we use a simple Forth script on ppc64 instead.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: db800b21d82a63eb88b06da9d1fb3d8a8e046aca
https://github.com/qemu/qemu/commit/db800b21d82a63eb88b06da9d1fb3d8a8e046aca
Author: David Gibson <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Add 2.8 machine type, set up compatibility macros
Now that 2.7 is released, create the pseries-2.8 machine type and add the
boilerplate compatiblity macro stuff. There's nothing new to put into the
2.7 compatiliby properties yet, but we'll need something eventually, so
we might as well get it ready now.
Signed-off-by: David Gibson <address@hidden>
Commit: 230bf719d3a3b144a4ffa441e5d6170ef0ad8999
https://github.com/qemu/qemu/commit/230bf719d3a3b144a4ffa441e5d6170ef0ad8999
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc/spapr: Move code related to "ibm,pa-features" to a separate function
The function spapr_populate_cpu_dt() has become quite big
already, and since we likely have to extend the pa-features
property for every new processor generation, it is nicer
if we put the related code into a separate function.
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4cbec30d769a73853b60dc7f275e6e7da9ab5162
https://github.com/qemu/qemu/commit/4cbec30d769a73853b60dc7f275e6e7da9ab5162
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc/spapr: Fix the selection of the processor features
The current code uses pa_features_206 for POWERPC_MMU_2_06, and
for everything else, it uses pa_features_207. This is bad in some
cases because there is also a "degraded" MMU version of ISA 2.06,
called POWERPC_MMU_2_06a, which should of course use the flags for
2.06 instead. And there is also the possibility that the user runs
the pseries machine with a POWER5+ or even 970 processor. In that
case we certainly do not want to set the flags for 2.07, and rather
simply skip the setting of the pa-features property instead.
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bac3bf287ab60e264b636f5f00c116a19b655762
https://github.com/qemu/qemu/commit/bac3bf287ab60e264b636f5f00c116a19b655762
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
Log Message:
-----------
ppc: Check the availability of transactional memory
KVM-PR currently does not support transactional memory, and the
implementation in TCG is just a fake. We should not announce TM
support in the ibm,pa-features property when running on such a
system, so disable it by default and only enable it if the KVM
implementation supports it (i.e. recent versions of KVM-HV).
These changes are based on some earlier work from Anton Blanchard
(thanks!).
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6358320228010e0425955ca6ed32ac878b24f12a
https://github.com/qemu/qemu/commit/6358320228010e0425955ca6ed32ac878b24f12a
Author: Ravi Bangoria <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Implement mfvsrld instruction
mfvsrld: Move From VSR Lower Doubleword
Signed-off-by: Ravi Bangoria <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b9731075b3c6417eca2bc14612688046c4b7f9e6
https://github.com/qemu/qemu/commit/b9731075b3c6417eca2bc14612688046c4b7f9e6
Author: Ravi Bangoria <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Implement mtvsrdd instruction
mtvsrdd: Move To VSR Double Doubleword
Signed-off-by: Ravi Bangoria <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f34001ec96ebc126aad49db4e3e01391b28ed264
https://github.com/qemu/qemu/commit/f34001ec96ebc126aad49db4e3e01391b28ed264
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target-ppc: improve lxvw4x implementation
Load 8byte at a time and manipulate.
Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+
Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+
Vector load results in (32-bit elements):
+----------+----------+----------+----------+
| 00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[dwg: Slight tweak to commit description]
Signed-off-by: David Gibson <address@hidden>
Commit: 0aec21d8fa1be9a2b57b0e018b36ba566508d21c
https://github.com/qemu/qemu/commit/0aec21d8fa1be9a2b57b0e018b36ba566508d21c
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target-ppc: improve stxvw4x implementation
Manipulate data and store 8bytes instead of 4bytes.
Vector (32-bit elements):
+----------+----------+----------+----------+
| 00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+
Store results in following:
Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+
Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1c0744190ca69732da13d49f6cb48e648dff9a40
https://github.com/qemu/qemu/commit/1c0744190ca69732da13d49f6cb48e648dff9a40
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: add lxvh8x instruction
lxvh8x: Load VSX Vector Halfword*8
Big-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+-------+-------+-------+-------+-------+-------+-------+-------+
Little-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 |
+-------+-------+-------+-------+-------+-------+-------+-------+
Vector load results in (16-bit elements):
+------+------+------+------+------+------+------+------+
| 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 |
+------+------+------+------+------+------+------+------+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[dwg: Tweak to commit description]
Signed-off-by: David Gibson <address@hidden>
Commit: 0b8ac648ecb02c4d157101c032518390b949e770
https://github.com/qemu/qemu/commit/0b8ac648ecb02c4d157101c032518390b949e770
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: add stxvh8x instruction
stxvh8x: Store VSX Vector Halfword*8
Vector (16-bit elements):
+------+------+------+------+------+------+------+------+
| 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 |
+------+------+------+------+------+------+------+------+
Store results in following:
Big-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+-------+-------+-------+-------+-------+-------+-------+-------+
Little-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 |
+-------+-------+-------+-------+-------+-------+-------+-------+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[dwg: Tweak commit description]
Signed-off-by: David Gibson <address@hidden>
Commit: 8ee38face981c0da805a35e681cfe141191a3569
https://github.com/qemu/qemu/commit/8ee38face981c0da805a35e681cfe141191a3569
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: add lxvb16x instruction
lxvb16x: Load VSX Vector Byte*16
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector load results in (8-bit elements):
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f3333ce0b50924cf1b3abe2802789125d91e6474
https://github.com/qemu/qemu/commit/f3333ce0b50924cf1b3abe2802789125d91e6474
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: add stxvb16x instruction
stxvb16x: Store VSX Vector Byte*16
Vector (8-bit elements):
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Store results in following:
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4aaefd93b9a7f5fdef83a757702b228d2144112a
https://github.com/qemu/qemu/commit/4aaefd93b9a7f5fdef83a757702b228d2144112a
Author: Avinesh Kumar <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: fix invalid mask - cmpl, bctar
cmpl: invalid bit mask should be 0x00400001
bctar: invalid bit mask should be 0x0000E000
Signed-off-by: Avinesh Kumar <address@hidden>
Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0fa59364348e9cb52c48b0d83a1ceaed840854aa
https://github.com/qemu/qemu/commit/0fa59364348e9cb52c48b0d83a1ceaed840854aa
Author: Rajalakshmi Srinivasaraghavan <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: add vector compare not equal instructions
The following vector compare not equal instructions are added from ISA 3.0.
vcmpneb - Vector Compare Not Equal Byte
vcmpneh - Vector Compare Not Equal Halfword
vcmpnew - Vector Compare Not Equal Word
Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4879538c99117e249ceb092a2ec0828d23aff01e
https://github.com/qemu/qemu/commit/4879538c99117e249ceb092a2ec0828d23aff01e
Author: Rajalakshmi Srinivasaraghavan <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: add vclzlsbb/vctzlsbb instructions
The following vector instructions are added from ISA 3.0.
vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte
Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1a136cdce078c32f5e8a556d43cc0af8614c2d8d
https://github.com/qemu/qemu/commit/1a136cdce078c32f5e8a556d43cc0af8614c2d8d
Author: Ravi Bangoria <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Implement mtvsrws instruction
mtvsrws: Move To VSR Word & Splat
Signed-off-by: Ravi Bangoria <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 835c42d34e0547180babaee7036c532a0e6977d7
https://github.com/qemu/qemu/commit/835c42d34e0547180babaee7036c532a0e6977d7
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add two more ppc related files
The file hw/intc/heathrow_pic.c belongs to the Old World Mac
machine, and pc-bios/ppc_rom.bin belongs to the PReP machine.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 96c9cff0ab986f3a0606e1a96c5b00e6a7c675c6
https://github.com/qemu/qemu/commit/96c9cff0ab986f3a0606e1a96c5b00e6a7c675c6
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
target-ppc/kvm: Add a wrapper function to check for KVM-PR
It makes more sense if we have a proper function to check
for KVM-PR than to check for the GET_PVINFO extension all
over the place.
Signed-off-by: Thomas Huth <address@hidden>
[dwg: Expanded a comment to discourage overuse of this function]
Signed-off-by: David Gibson <address@hidden>
Commit: 7f516c9675285298826d4ef20ce1a093b13caf89
https://github.com/qemu/qemu/commit/7f516c9675285298826d4ef20ce1a093b13caf89
Author: Thomas Huth <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too
Transactional memory is also supported on POWER8 KVM-HV if the
KVM_CAP_PPC_HTM is not available in the kernel yet, so add a hack
to allow TM here, too.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2020b67d851affd9dd8b3732a5290d90be6187d1
https://github.com/qemu/qemu/commit/2020b67d851affd9dd8b3732a5290d90be6187d1
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-05 (Wed, 05 Oct 2016)
Changed paths:
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: fix vmx instruction type/type2
A few of the new instructions added inadvertently changed the type of
old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form
declaration.
commit: b5d569a1 (target-ppc: add vector extract instructions)
commit: e7b1e06f (target-ppc: add vector insert instructions)
commit: 3aa56a19 (target-ppc: add vector compare not equal instructions)
New ISA 3.0 instructions added:
vextractub PPC_NONE PPC2_ISA300
vextractuh PPC_NONE PPC2_ISA300
vextractuw PPC_NONE PPC2_ISA300
vinsertb PPC_NONE PPC2_ISA300
vinserth PPC_NONE PPC2_ISA300
vinsertw PPC_NONE PPC2_ISA300
vcmpneb PPC_NONE PPC2_ISA300
vcmpneh PPC_NONE PPC2_ISA300
vcmpnew PPC_NONE PPC2_ISA300
Affected older instructions:
vspltb PPC_ALTIVEC PPC_NONE
vsplth PPC_ALTIVEC PPC_NONE
vspltw PPC_ALTIVEC PPC_NONE
vspltisb PPC_ALTIVEC PPC_NONE
vspltish PPC_ALTIVEC PPC_NONE
vspltisw PPC_ALTIVEC PPC_NONE
vcmpequb PPC_ALTIVEC PPC_NONE
vcmpequh PPC_ALTIVEC PPC_NONE
vcmpequw PPC_ALTIVEC PPC_NONE
Change the instruction type/type2 for the older instructions back to
what it was(PPC_ALTIVEC).
CC: Rajalakshmi Srinivasaraghavan <address@hidden>
Reported-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cf716b31cba278a6dbff585d58fa29d1ae2fe334
https://github.com/qemu/qemu/commit/cf716b31cba278a6dbff585d58fa29d1ae2fe334
Author: Laurent Vivier <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M tests/Makefile.include
M tests/libqos/pci-pc.c
A tests/libqos/pci-spapr.c
A tests/libqos/pci-spapr.h
M tests/libqos/pci.c
M tests/libqos/rtas.c
M tests/libqos/rtas.h
Log Message:
-----------
libqos: add PPC64 PCI support
Signed-off-by: Laurent Vivier <address@hidden>
[dwg: Fixed build problem on 32-bit hosts]
Signed-off-by: David Gibson <address@hidden>
Commit: 2ecd7e2f25a57e8966a15ee50a0afacd4ec067da
https://github.com/qemu/qemu/commit/2ecd7e2f25a57e8966a15ee50a0afacd4ec067da
Author: Laurent Vivier <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M tests/e1000e-test.c
M tests/i440fx-test.c
M tests/ide-test.c
M tests/ivshmem-test.c
M tests/libqos/ahci.c
M tests/libqos/libqos-pc.c
M tests/libqos/libqos-spapr.c
M tests/libqos/libqos.c
M tests/libqos/libqos.h
M tests/libqos/pci-pc.c
M tests/libqos/pci-pc.h
M tests/q35-test.c
M tests/rtl8139-test.c
M tests/tco-test.c
M tests/usb-hcd-ehci-test.c
M tests/usb-hcd-uhci-test.c
M tests/vhost-user-test.c
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-net-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
libqos: add PCI management in qtest_vboot()/qtest_shutdown()
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 61ae5cf3a2e1a7764a60fec69cd8731516d5fb83
https://github.com/qemu/qemu/commit/61ae5cf3a2e1a7764a60fec69cd8731516d5fb83
Author: Laurent Vivier <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M tests/libqos/libqos-pc.c
M tests/libqos/libqos-spapr.c
M tests/libqos/libqos.c
M tests/libqos/libqos.h
M tests/rtas-test.c
Log Message:
-----------
libqos: use generic qtest_shutdown()
Machine specific shutdown function can be registered by
the machine specific qtest_XXX_boot() if needed.
So we will not have to test twice the architecture (on boot and on
shutdown) if the test can be run on several architectures.
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: aa9026fd5e3d58cdaf3b28b60a4639f69c7bfff6
https://github.com/qemu/qemu/commit/aa9026fd5e3d58cdaf3b28b60a4639f69c7bfff6
Author: Laurent Vivier <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M tests/Makefile.include
M tests/usb-hcd-uhci-test.c
Log Message:
-----------
tests: enable ohci/uhci/xhci tests on PPC64
Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e17a87792d4886d2a508672c1639df3c1d40f1d1
https://github.com/qemu/qemu/commit/e17a87792d4886d2a508672c1639df3c1d40f1d1
Author: Greg Kurz <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr: fix check of cpu alias name in spapr_get_cpu_core_type()
If the user passes an alias name and a property to -cpu, QEMU fails to
find the CPU definition and exits.
$ qemu-system-ppc64 -cpu POWER8E,compat=power7
qemu-system-ppc64: Unable to find sPAPR CPU Core definition
This happens because spapr_get_cpu_core_type() passes the full string from
the command line (i.e. "POWER8E,compat=power7") to ppc_cpu_lookup_alias(),
instead of the alias name piece only (i.e. "POWER8E").
The fix is to pass model_pieces[0] to ppc_cpu_lookup_alias().
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ef6c47f1d7c242cb0ce66fcaab4ebcd94ad2a134
https://github.com/qemu/qemu/commit/ef6c47f1d7c242cb0ce66fcaab4ebcd94ad2a134
Author: Thomas Huth <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M tests/pxe-test.c
Log Message:
-----------
tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test
SLOF is unfortunately quite slow when running with TCG, so
the pxe test is also performing rather slow here. By using
"-nodefaults" we can disable some devices (vscsi) that we
are not interested in here, so that SLOF does not have to
scan them during boot and thus starts up a little bit faster.
The ppc64 pxe-test now only takes 27 seconds on my laptop
instead of 33 seconds.
The "-nodefaults" flag seems to work fine for the x86 tests,
too, so it is added here unconditionally here (though there
is no speed-up on x86 by using this flag).
Suggested-by: Paolo Bonzini <address@hidden>
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3daa4a9f9580ffda47df93c7c53371af226bf970
https://github.com/qemu/qemu/commit/3daa4a9f9580ffda47df93c7c53371af226bf970
Author: Thomas Huth <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine
A couple of distributors are compiling their distributions
with "-mcpu=power8" for ppc64le these days, so the user sooner
or later runs into a crash there when not explicitely specifying
the "-cpu POWER8" option to QEMU (which is currently using POWER7
for the "pseries" machine by default). Due to this reason, the
linux-user target already switched to POWER8 a while ago (see commit
de3f1b98410e0d5b406a0df3a48547b559d18602). Since the softmmu target
of course has the same problem, we should switch there to POWER8 for
the newer machine types, too.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e902754e3d0890945ddcc1b33748ed73762ddb8d
https://github.com/qemu/qemu/commit/e902754e3d0890945ddcc1b33748ed73762ddb8d
Author: Peter Maydell <address@hidden>
Date: 2016-10-06 (Thu, 06 Oct 2016)
Changed paths:
M MAINTAINERS
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/scsi/spapr_vscsi.c
M hw/scsi/trace-events
M include/hw/ppc/spapr.h
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
M target-ppc/translate.c
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
M tests/Makefile.include
M tests/boot-sector.c
M tests/e1000e-test.c
M tests/i440fx-test.c
M tests/ide-test.c
M tests/ivshmem-test.c
M tests/libqos/ahci.c
M tests/libqos/libqos-pc.c
M tests/libqos/libqos-spapr.c
M tests/libqos/libqos.c
M tests/libqos/libqos.h
M tests/libqos/pci-pc.c
M tests/libqos/pci-pc.h
A tests/libqos/pci-spapr.c
A tests/libqos/pci-spapr.h
M tests/libqos/pci.c
M tests/libqos/rtas.c
M tests/libqos/rtas.h
M tests/pxe-test.c
M tests/q35-test.c
M tests/rtas-test.c
M tests/rtl8139-test.c
M tests/tco-test.c
M tests/usb-hcd-ehci-test.c
M tests/usb-hcd-uhci-test.c
M tests/vhost-user-test.c
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-net-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20161006' into
staging
ppc patch queue 2016-10-06
Currently accumulated target-ppc and spapr machine related patches.
- More POWER9 instruction implementations
- Additional test case / enabling of test cases for Power
- Assorted fixes
# gpg: Signature made Thu 06 Oct 2016 07:05:07 BST
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.8-20161006: (29 commits)
hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine
tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test
spapr: fix check of cpu alias name in spapr_get_cpu_core_type()
tests: enable ohci/uhci/xhci tests on PPC64
libqos: use generic qtest_shutdown()
libqos: add PCI management in qtest_vboot()/qtest_shutdown()
libqos: add PPC64 PCI support
target-ppc: fix vmx instruction type/type2
target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too
target-ppc/kvm: Add a wrapper function to check for KVM-PR
MAINTAINERS: Add two more ppc related files
target-ppc: Implement mtvsrws instruction
target-ppc: add vclzlsbb/vctzlsbb instructions
target-ppc: add vector compare not equal instructions
target-ppc: fix invalid mask - cmpl, bctar
target-ppc: add stxvb16x instruction
target-ppc: add lxvb16x instruction
target-ppc: add stxvh8x instruction
target-ppc: add lxvh8x instruction
target-ppc: improve stxvw4x implementation
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/0bdb12c7c50e...e902754e3d08
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