[Qemu-commits] [qemu/qemu] 81fed1: STM32F205: Remove the individual devi

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[Qemu-commits] [qemu/qemu] 81fed1: STM32F205: Remove the individual devi

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 81fed1: STM32F205: Remove the individual device variables
Date:	Tue, 04 Oct 2016 06:30:07 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 81fed1d017d9460ac39e9ba775fcbe8bd90b1847
      
https://github.com/qemu/qemu/commit/81fed1d017d9460ac39e9ba775fcbe8bd90b1847
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/stm32f205_soc.c

  Log Message:
  -----------
  STM32F205: Remove the individual device variables

Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cbcb93e802076ecea9b3defe609ce4a45719e809
      
https://github.com/qemu/qemu/commit/cbcb93e802076ecea9b3defe609ce4a45719e809
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/timer/stm32f2xx_timer.c

  Log Message:
  -----------
  STM32F2xx: Display PWM duty cycle from timer

If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d1f711d4070155ec6b81d331169c52f1bd6a4f21
      
https://github.com/qemu/qemu/commit/d1f711d4070155ec6b81d331169c52f1bd6a4f21
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/Makefile.objs
    A hw/adc/Makefile.objs
    A hw/adc/stm32f2xx_adc.c
    A include/hw/adc/stm32f2xx_adc.h

  Log Message:
  -----------
  STM32F2xx: Add the ADC device

Add the STM32F2xx ADC device. This device randomly
generates values on each read.

This also includes creating a hw/adc directory.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5ae74402d1f3221ed26936c4b9febc7e69ecdc5b
      
https://github.com/qemu/qemu/commit/5ae74402d1f3221ed26936c4b9febc7e69ecdc5b
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/ssi/Makefile.objs
    A hw/ssi/stm32f2xx_spi.c
    A include/hw/ssi/stm32f2xx_spi.h

  Log Message:
  -----------
  STM32F2xx: Add the SPI device

Add the STM32F2xx SPI device.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1b2556776531ba3f492f5ce9f6ae769f3b4e7a82
      
https://github.com/qemu/qemu/commit/1b2556776531ba3f492f5ce9f6ae769f3b4e7a82
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/core/Makefile.objs
    A hw/core/or-irq.c
    A include/hw/or-irq.h

  Log Message:
  -----------
  irq: Add a new irq device that allows the ORing of lines

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b63041c8f6b1ad2332c6c8f458f26b34325613bf
      
https://github.com/qemu/qemu/commit/b63041c8f6b1ad2332c6c8f458f26b34325613bf
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/stm32f205_soc.c
    M include/hw/arm/stm32f205_soc.h

  Log Message:
  -----------
  STM32F205: Connect the ADC devices

Connect the ADC devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 540a8f34b4f018570a0bbd86975d41dee0d9510c
      
https://github.com/qemu/qemu/commit/540a8f34b4f018570a0bbd86975d41dee0d9510c
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/stm32f205_soc.c
    M include/hw/arm/stm32f205_soc.h

  Log Message:
  -----------
  STM32F205: Connect the SPI devices

Connect the SPI devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1f8193bb41283923710f23faf436b6b0a7bb3f2
      
https://github.com/qemu/qemu/commit/a1f8193bb41283923710f23faf436b6b0a7bb3f2
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add Alistair to the maintainers list

Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8cb2d2db50eed3e708b9504891735e78f00e6e3d
      
https://github.com/qemu/qemu/commit/8cb2d2db50eed3e708b9504891735e78f00e6e3d
  Author: Vijay Kumar B <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/mainstone.c

  Log Message:
  -----------
  mainstone: Fix incorrect key mapping for Enter key.

According to the manual the (5, 5) corresponds to backspace key, and
not Enter key. Linux kernel maps (5, 4) to the enter key. Fixing it up
to match the mapping in the Linux kernel.

Signed-off-by: Vijay Kumar B. <address@hidden>
Reviewed-by: Deepak S. <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c74e95bf87f9fb2187e7b1baa427a7b74d69ccd
      
https://github.com/qemu/qemu/commit/0c74e95bf87f9fb2187e7b1baa427a7b74d69ccd
  Author: Vijay Kumar B <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/mainstone.c

  Log Message:
  -----------
  mainstone: Add mapping for dot, slash and backspace.

Add missed out mappings. These mappings are from the "Intel PXA27x
Processor Developer's Kit User Guide".

Signed-off-by: Vijay Kumar B. <address@hidden>
Reviewed-by: Deepak S. <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e9d9ee234f852026d58b275d89a0350cb9ddbc01
      
https://github.com/qemu/qemu/commit/e9d9ee234f852026d58b275d89a0350cb9ddbc01
  Author: Jakub Jermar <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/integratorcp.c

  Log Message:
  -----------
  hw/arm: Fix Integrator/CM initialization

Initialization of a class instance cannot depend on its own properties
as these are not yet set.  Move parts of integratorcm_init() that depend
on the "memsz" property to the newly added integratorcm_realize().

This fixes: https://bugs.launchpad.net/qemu/+bug/1624726

Signed-off-by: Jakub Jermar <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a321bb51fa208a0a3b421ff9944558b936cc1e5a
      
https://github.com/qemu/qemu/commit/a321bb51fa208a0a3b421ff9944558b936cc1e5a
  Author: Dr. David Alan Gilbert <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/input/tsc2005.c

  Log Message:
  -----------
  vmstateify tsc2005

I've converted the fields in it's main data structure
to fixed size types in ways that look sane.

Signed-off-by: Dr. David Alan Gilbert <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fa53b7f047d2c39311d4160f29a20801c1f7af3c
      
https://github.com/qemu/qemu/commit/fa53b7f047d2c39311d4160f29a20801c1f7af3c
  Author: Dr. David Alan Gilbert <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/input/tsc210x.c

  Log Message:
  -----------
  vmstateify tsc210x

I'm now saving all 3 of the pll entries; only 2 were saved before.
There are a couple of times that were previously stored as offsets
from 'now' calculated before saving;  with vmstate it's easier
to store the 'now' and fix it up on reload.

Signed-off-by: Dr. David Alan Gilbert <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 96b0439bbe2083c10308ce91860e2129f52bc1ae
      
https://github.com/qemu/qemu/commit/96b0439bbe2083c10308ce91860e2129f52bc1ae
  Author: Andrew Jones <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: add 2.8 machine type

Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d19a4d4ef448e736d341df47bd1adc78c8e40814
      
https://github.com/qemu/qemu/commit/d19a4d4ef448e736d341df47bd1adc78c8e40814
  Author: Eric Auger <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/intc/arm_gic_kvm.c
    M hw/intc/arm_gicv3_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gic(v3)_kvm: Initialize gsi routing

Advertise gsi routing and set up irqchip routing entries for
GIC SPIs.

This is not mandated as long as MSI routing is not used
(because the kernel sets a default irqchip routing table).
However once MSI routing gets used (for VIRTIO-PCI vhost for
example), the first call to KVM_SET_GSI_ROUTING overrides the
kernel default irqchip table.

If no routing entry exists for the GSI, any IRQFD signaling for
this GSI will fail.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 386ce3c7fc6bf384eaf78cfbb766c015c26bf9ca
      
https://github.com/qemu/qemu/commit/386ce3c7fc6bf384eaf78cfbb766c015c26bf9ca
  Author: Pavel Fedin <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/arm_gicv3_its_common.c
    A include/hw/intc/arm_gicv3_its_common.h
    M target-arm/kvm_arm.h

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement ITS base class

This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.

Signed-off-by: Pavel Fedin <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1b20616f261f28ef971c2b40066b968206104501
      
https://github.com/qemu/qemu/commit/1b20616f261f28ef971c2b40066b968206104501
  Author: Eric Auger <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M target-arm/kvm_arm.h
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: move gicv3_class_name from machine to kvm_arm.h

Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Suggested-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 767a554a0c752cff1e1d17550aefd4e9dca881d6
      
https://github.com/qemu/qemu/commit/767a554a0c752cff1e1d17550aefd4e9dca881d6
  Author: Pavel Fedin <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c
    M kvm-stub.c

  Log Message:
  -----------
  kvm-all: Pass requester ID to MSI routing functions

Introduce global kvm_msi_use_devid flag plus associated
kvm_msi_devid_required() macro. Passes the device ID,
if needed, while building the MSI route entry. Device IDs are
required by the ARM GICv3 ITS (IRQ remapping function is based on
this information).

Signed-off-by: Pavel Fedin <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c9f302ea2906eb763cd175134e34d23ed4fea6a
      
https://github.com/qemu/qemu/commit/0c9f302ea2906eb763cd175134e34d23ed4fea6a
  Author: Pavel Fedin <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/arm_gicv3_its_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation

The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)

the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
difference with GICv2M. Direct mapping cannot work with ITS since
the content of the MSI data is not the target interrupt ID but an
eventd id.

GSI routing is advertised (kvm_gsi_routing_allowed) as well as
msi/irqfd signaling (kvm_msi_via_irqfd_allowed).

The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first
kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI
ioctl.

Signed-off-by: Pavel Fedin <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 02f9873180c0893dfe79854ae80cc4b02f862237
      
https://github.com/qemu/qemu/commit/02f9873180c0893dfe79854ae80cc4b02f862237
  Author: Pavel Fedin <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  arm/virt: Add ITS to the virt board

If supported by the configuration, ITS will be added automatically.

This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.

Signed-off-by: Pavel Fedin <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1c2e4ea7b645a127ee6d13a7072f6669d4d826c7
      
https://github.com/qemu/qemu/commit/1c2e4ea7b645a127ee6d13a7072f6669d4d826c7
  Author: Shannon Zhao <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M include/hw/acpi/acpi-defs.h

  Log Message:
  -----------
  ACPI: Add GIC Interrupt Translation Service Structure definition

ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure.
Here we add the definition of the Structure.

Signed-off-by: Shannon Zhao <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 13e5c54d30312aef7ac7a265209e39f4655be211
      
https://github.com/qemu/qemu/commit/13e5c54d30312aef7ac7a265209e39f4655be211
  Author: Shannon Zhao <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table

If GIC ITS is supported, add description in ACPI MADT table, then guest
could use ITS when booting with ACPI.

Signed-off-by: Shannon Zhao <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e481a1f63c93344974f799a5e38df980ef5f7f9c
      
https://github.com/qemu/qemu/commit/e481a1f63c93344974f799a5e38df980ef5f7f9c
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M MAINTAINERS
    M hw/core/Makefile.objs
    A hw/core/generic-loader.c
    A include/hw/core/generic-loader.h

  Log Message:
  -----------
  generic-loader: Add a generic loader

Add a generic loader to QEMU which can be used to load images or set
memory values.

Internally inside QEMU this is a device. It is a strange device that
provides no hardware interface but allows QEMU to monkey patch memory
specified when it is created. To be able to do this it has a reset
callback that does the memory operations.

This device allows the user to monkey patch memory. To be able to do
this it needs a backend to manage the datas, the same as other
memory-related devices. In this case as the backend is so trivial we
have merged it with the frontend instead of creating and maintaining a
seperate backend.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Acked-by: Markus Armbruster <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 03bf19535c2581937397e608335c111c03895ba8
      
https://github.com/qemu/qemu/commit/03bf19535c2581937397e608335c111c03895ba8
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    A docs/generic-loader.txt

  Log Message:
  -----------
  docs: Add a generic loader explanation document

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 79b2ac8f28748b09816d09bd62a2b49ddc01ebeb
      
https://github.com/qemu/qemu/commit/79b2ac8f28748b09816d09bd62a2b49ddc01ebeb
  Author: Alistair Francis <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  cadence_gem: Fix priority queue out of bounds access

There was an error with some of the register implementation assuming
there are 16 priority queues supported when the IP only supports 8. This
patch corrects the registers to only support 8 queues.

Signed-off-by: Alistair Francis <address@hidden>
Reported-by: Paolo Bonzini <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 173ff58580b383a7841b18fddb293038c9d40d1c
      
https://github.com/qemu/qemu/commit/173ff58580b383a7841b18fddb293038c9d40d1c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Fix decoding of iss_sf in disas_ld_lit

Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.

If cleared it specifies 32 bits.
If set it specifies 64 bits.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: tweaked phrasing per on-list discussion]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0
      
https://github.com/qemu/qemu/commit/9b6a3ea7a699594162ed3d11e4e04b98568dc5c0
  Author: Peter Maydell <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6

In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
branch, so the computed new value is written to r15 as a normal
value. The architecture says that in this case, bits [1:0] of
the value written must be ignored if we are in ARM mode (or
bit [0] ignored if in Thumb mode); this is a change from the
ARMv4/v5 specification that behaviour is UNPREDICTABLE.
Use the correct mask on the PC value when doing a non-interworking
store to PC.

A popular library used on RaspberryPi uses this instruction
as part of a trick to determine whether it is running on
ARMv6 or ARMv7, and we were mishandling the sequence.

Fixes bug: https://bugs.launchpad.net/bugs/1625295

Reported-by: <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 6e11eb2d2b96790e647aa4c744ed2ed03a77fbbd
      
https://github.com/qemu/qemu/commit/6e11eb2d2b96790e647aa4c744ed2ed03a77fbbd
  Author: Peter Maydell <address@hidden>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    A docs/generic-loader.txt
    M hw/Makefile.objs
    A hw/adc/Makefile.objs
    A hw/adc/stm32f2xx_adc.c
    M hw/arm/integratorcp.c
    M hw/arm/mainstone.c
    M hw/arm/stm32f205_soc.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/core/Makefile.objs
    A hw/core/generic-loader.c
    A hw/core/or-irq.c
    M hw/input/tsc2005.c
    M hw/input/tsc210x.c
    M hw/intc/Makefile.objs
    M hw/intc/arm_gic_kvm.c
    A hw/intc/arm_gicv3_its_common.c
    A hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/net/cadence_gem.c
    M hw/ssi/Makefile.objs
    A hw/ssi/stm32f2xx_spi.c
    M hw/timer/stm32f2xx_timer.c
    M include/hw/acpi/acpi-defs.h
    A include/hw/adc/stm32f2xx_adc.h
    M include/hw/arm/stm32f205_soc.h
    A include/hw/core/generic-loader.h
    A include/hw/intc/arm_gicv3_its_common.h
    A include/hw/or-irq.h
    A include/hw/ssi/stm32f2xx_spi.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M kvm-stub.c
    M target-arm/kvm_arm.h
    M target-arm/machine.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161004' 
into staging

target-arm queue:
 * Netduino 2 improvements (SPI, ADC devices)
 * fix some Mainstone key mappings
 * vmstateify tsc210x, tsc2005
 * virt: add 2.8 machine type
 * virt: support in-kernel GICv3 ITS
 * generic-loader device
 * A64: fix iss_sf decoding in disas_ld_lit
 * correctly handle 'sub pc, pc, 1' for ARMv6

# gpg: Signature made Tue 04 Oct 2016 13:41:34 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20161004: (27 commits)
  target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
  target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
  cadence_gem: Fix priority queue out of bounds access
  docs: Add a generic loader explanation document
  generic-loader: Add a generic loader
  ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
  ACPI: Add GIC Interrupt Translation Service Structure definition
  arm/virt: Add ITS to the virt board
  hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
  kvm-all: Pass requester ID to MSI routing functions
  target-arm: move gicv3_class_name from machine to kvm_arm.h
  hw/intc/arm_gicv3_its: Implement ITS base class
  hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
  hw/arm/virt: add 2.8 machine type
  vmstateify tsc210x
  vmstateify tsc2005
  hw/arm: Fix Integrator/CM initialization
  mainstone: Add mapping for dot, slash and backspace.
  mainstone: Fix incorrect key mapping for Enter key.
  MAINTAINERS: Add Alistair to the maintainers list
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1bb47107057c...6e11eb2d2b96
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