[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH v4 18/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty
From: |
Jinjie Ruan |
Subject: |
[RFC PATCH v4 18/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty |
Date: |
Wed, 28 Feb 2024 09:29:42 +0000 |
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pending irq is NMI in gicv3_redist_update_noirqset and
gicv3_update_noirqset. And In irqbetter(), only a non-NMI with the same
priority and a smaller interrupt number can be preempted but not NMI.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
v4:
- Replace is_nmi with has_superprio to not a mix NMI and superpriority.
- Update the comment in irqbetter().
- Extract gicv3_get_priority() to avoid code repeat.
---
v3:
- Add missing brace
---
hw/intc/arm_gicv3.c | 71 ++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 63 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 0b8f79a122..1d16a53b23 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -21,7 +21,8 @@
#include "hw/intc/arm_gicv3.h"
#include "gicv3_internal.h"
-static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
+static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio,
+ bool has_superprio)
{
/* Return true if this IRQ at this priority should take
* precedence over the current recorded highest priority
@@ -33,11 +34,24 @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t
prio)
if (prio < cs->hppi.prio) {
return true;
}
+
+ /*
+ * Current highest prioirity pending interrupt is an IRQ without
+ * superpriority, the new IRQ with superpriority has same priority
+ * should signal to the CPU as it have the priority higher than
+ * the labelled 0x80 or 0x00.
+ */
+ if (prio == cs->hppi.prio && !cs->hppi.superprio && has_superprio) {
+ return true;
+ }
+
/* If multiple pending interrupts have the same priority then it is an
* IMPDEF choice which of them to signal to the CPU. We choose to
- * signal the one with the lowest interrupt number.
+ * signal the one with the lowest interrupt number if they don't have
+ * superpriority.
*/
- if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
+ if (prio == cs->hppi.prio && !cs->hppi.superprio &&
+ !has_superprio && irq <= cs->hppi.irq) {
return true;
}
return false;
@@ -129,6 +143,35 @@ static uint32_t gicr_int_pending(GICv3CPUState *cs)
return pend;
}
+static bool gicv3_get_priority(GICv3CPUState *cs, bool is_redist,
+ uint32_t superprio, uint8_t *prio, int irq)
+{
+ bool has_superprio = false;
+
+ if (superprio) {
+ has_superprio = true;
+
+ /* DS = 0 & Non-secure NMI */
+ if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
+ ((is_redist && extract32(cs->gicr_igroupr0, irq, 1)) ||
+ (!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) {
+ *prio = 0x80;
+ } else {
+ *prio = 0x0;
+ }
+ } else {
+ has_superprio = false;
+
+ if (is_redist) {
+ *prio = cs->gicr_ipriorityr[irq];
+ } else {
+ *prio = cs->gic->gicd_ipriority[irq];
+ }
+ }
+
+ return has_superprio;
+}
+
/* Update the interrupt status after state in a redistributor
* or CPU interface has changed, but don't tell the CPU i/f.
*/
@@ -141,6 +184,8 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
uint8_t prio;
int i;
uint32_t pend;
+ uint32_t superprio = 0;
+ bool has_superprio = false;
/* Find out which redistributor interrupts are eligible to be
* signaled to the CPU interface.
@@ -152,10 +197,13 @@ static void gicv3_redist_update_noirqset(GICv3CPUState
*cs)
if (!(pend & (1 << i))) {
continue;
}
- prio = cs->gicr_ipriorityr[i];
- if (irqbetter(cs, i, prio)) {
+ superprio = extract32(cs->gicr_isuperprio, i, 1);
+ has_superprio = gicv3_get_priority(cs, true, superprio, &prio, i);
+
+ if (irqbetter(cs, i, prio, has_superprio)) {
cs->hppi.irq = i;
cs->hppi.prio = prio;
+ cs->hppi.superprio = has_superprio;
seenbetter = true;
}
}
@@ -168,7 +216,7 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
(cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) &&
(cs->hpplpi.prio != 0xff)) {
- if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+ if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio, false)) {
cs->hppi.irq = cs->hpplpi.irq;
cs->hppi.prio = cs->hpplpi.prio;
cs->hppi.grp = cs->hpplpi.grp;
@@ -213,6 +261,8 @@ static void gicv3_update_noirqset(GICv3State *s, int start,
int len)
int i;
uint8_t prio;
uint32_t pend = 0;
+ uint32_t superprio = 0;
+ bool has_superprio = false;
assert(start >= GIC_INTERNAL);
assert(len > 0);
@@ -240,10 +290,15 @@ static void gicv3_update_noirqset(GICv3State *s, int
start, int len)
*/
continue;
}
- prio = s->gicd_ipriority[i];
- if (irqbetter(cs, i, prio)) {
+
+ superprio = *gic_bmp_ptr32(s->superprio, i);
+ superprio = superprio & (1 << (i & 0x1f));
+ has_superprio = gicv3_get_priority(cs, false, superprio, &prio, i);
+
+ if (irqbetter(cs, i, prio, has_superprio)) {
cs->hppi.irq = i;
cs->hppi.prio = prio;
+ cs->hppi.superprio = has_superprio;
cs->seenbetter = true;
}
}
--
2.34.1
- [RFC PATCH v4 06/22] target/arm: Add support for Non-maskable Interrupt, (continued)
- [RFC PATCH v4 06/22] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 20/22] hw/intc/arm_gicv3: Report the VNMI interrupt, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 16/22] hw/intc: Enable FEAT_GICv3_NMI Feature, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 19/22] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 09/22] target/arm: Handle PSTATE.ALLINT on taking an exception, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 13/22] hw/intc/arm_gicv3: Add irq superpriority information, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 03/22] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 21/22] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 10/22] hw/arm/virt: Wire NMI and VNMI irq lines from GIC to CPU, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 18/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty,
Jinjie Ruan <=
- [RFC PATCH v4 12/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/02/28