[PATCH v2 0/3] Add "num-prio-bits" property for Cortex-M devices

[Samuel Tardieu]

This patch series builds on a discussion initiated by Anton Kochkov on
this list in 2022. It allows setting the appropriate number of priority
bits for Cortex-M devices. For example, FreeRTOS checks at startup that
the right number of priority bits is available in order to guarantee
its runtime structures safety. They have added a configuration option
to disable this check when running on QEMU because QEMU always use 2
bits for Cortex-M0/M0+/M1 and 8 bits for other devices.

While this change allows the number of priority bits to be properly
configured, it keeps the same default as before in order to preserve
backward compatibility unless the SoC configures the exact value.

Changes from v1:
- Add support for the STM32L4x5 SOC family (which is currently
  under review for integration) and fix the Based-on: trailer
  in the cover letter.
- Fix a typo in one of the commit messages ("compatibility")

Based-on: <20231221213838.54944-1-ines.varhol@telecom-paris.fr>
([PATCH v4 0/2] Add minimal support for the B-L475E-IOT01A board)

Samuel Tardieu (3):
  hw/intc/armv7m_nvic: add "num-prio-bits" property
  hw/arm/armv7m: alias the NVIC "num-prio-bits" property
  hw/arm/socs: configure priority bits for existing SOCs

 hw/arm/armv7m.c        |  2 ++
 hw/arm/stellaris.c     |  2 ++
 hw/arm/stm32f100_soc.c |  1 +
 hw/arm/stm32f205_soc.c |  1 +
 hw/arm/stm32f405_soc.c |  1 +
 hw/arm/stm32l4x5_soc.c |  1 +
 hw/intc/armv7m_nvic.c  | 23 ++++++++++++++++++++++-
 7 files changed, 30 insertions(+), 1 deletion(-)

-- 
2.42.0