Re: [PATCH v2] target/arm: update the cortex-a15 MIDR to latest rev

[Peter Maydell]

On Mon, 10 Oct 2022 at 16:32, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> QEMU doesn't model micro-architectural details which includes most
> chip errata. The ARM_ERRATA_798181 work around in the Linux
> kernel (see erratum_a15_798181_init) currently detects QEMU's
> cortex-a15 as broken and triggers additional expensive TLB flushes as
> a result.
>
> Change the MIDR to report what the latest silicon would (r4p0). We
> explicitly set the IMPDEF revidr bits to 0 because we don't need to
> set anything other than the silicon revision to indicate these flushes
> are not needed. This cuts about 5s from my Debian kernel boot with the
> latest 6.0rc1 kernel (29s->24s).



Applied to target-arm.next, thanks.

-- PMM