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[Qemu-arm] [PATCH 3/4] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBP
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 3/4] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} |
Date: |
Mon, 20 May 2019 17:28:08 +0100 |
In ich_vmcr_write() we enforce "writes of BPR fields to less than
their minimum sets them to the minimum" by doing a "read vbpr and
write it back" operation. A typo here meant that we weren't handling
writes to these fields correctly, because we were reading from VBPR0
but writing to VBPR1.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_cpuif.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index cbad6037f19..000bdbd6247 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2366,7 +2366,7 @@ static void ich_vmcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
* by reading and writing back the fields.
*/
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
gicv3_cpuif_virt_update(cs);
--
2.20.1
- [Qemu-arm] [PATCH 0/4] hw/intc/arm_gicv3: Four simple bugfixes, Peter Maydell, 2019/05/20
- [Qemu-arm] [PATCH 1/4] hw/intc/arm_gicv3: Fix decoding of ID register range, Peter Maydell, 2019/05/20
- [Qemu-arm] [PATCH 2/4] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1, Peter Maydell, 2019/05/20
- [Qemu-arm] [PATCH 3/4] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1},
Peter Maydell <=
- [Qemu-arm] [PATCH 4/4] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3, Peter Maydell, 2019/05/20
- Re: [Qemu-arm] [PATCH 0/4] hw/intc/arm_gicv3: Four simple bugfixes, Peter Maydell, 2019/05/23