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Re: [Qemu-arm] [PATCH 0/2] target/arm: fix some ATS* bugs


From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH 0/2] target/arm: fix some ATS* bugs
Date: Fri, 2 Nov 2018 17:55:26 +0000

Ping for code review, please?

thanks
-- PMM

On 16 October 2018 at 10:37, Peter Maydell <address@hidden> wrote:
> This small patchset fixes a couple of bugs in our ATS insn
> handling:
>  * for faults reported to the 64-bit PAR we were not
>    setting the S and PTW bits to indicate stage 2
>    fault information
>    (NB: stage 2 faults aren't reported with 32-bit
>    PAR formats so there's no need to change the 32-bit
>    code path)
>  * ATS1Hx were implementing the wrong thing (doing a
>    stage 2 lookup rather than an EL2 stage 1 lookup)
>
> The major missing bit of ATS at the moment is that a stage
> 2 fault during execution of an NS-EL1 ATS insn that asks
> for a stage 1 lookup should cause a trap to EL2. I started
> to sketch out some code to do that, but I realised by
> putting an assert() in it that I didn't have any guests
> that actually hit the problem, so put it on the back burner.
> If anybody does hit that missing feature, feel free to send
> me a test case :-)
>
> Based-on: <address@hidden>
> ("[PATCH 00/10] target/arm: more HCR bits, improve syndrome reporting")
> but only to avoid a textual conflict in the patch context.
>
> thanks
> -- PMM
>
> Peter Maydell (2):
>   target/arm: Set S and PTW in 64-bit PAR format
>   target/arm: Fix ATS1Hx instructions
>
>  target/arm/helper.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)



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