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[Qemu-arm] [PATCH v2 2/5] target/arm: Fill in ARMISARegisters for kvm64
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 2/5] target/arm: Fill in ARMISARegisters for kvm64 |
Date: |
Fri, 2 Nov 2018 14:54:30 +0000 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/kvm64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 5de8ff0ac5..d4d4e63140 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -443,17 +443,40 @@ static inline void unset_feature(uint64_t *features, int
feature)
*features &= ~(1ULL << feature);
}
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
+{
+ uint64_t ret;
+ struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
+ int err;
+
+ assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
+ err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
+ if (err < 0) {
+ return -1;
+ }
+ *pret = ret;
+ return 0;
+}
+
+static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
+{
+ struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
+
+ assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
+ return ioctl(fd, KVM_GET_ONE_REG, &idreg);
+}
+
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{
/* Identify the feature bits corresponding to the host CPU, and
* fill out the ARMHostCPUClass fields accordingly. To do this
* we have to create a scratch VM, create a single CPU inside it,
* and then query that CPU for the relevant ID registers.
- * For AArch64 we currently don't care about ID registers at
- * all; we just want to know the CPU type.
*/
int fdarray[3];
uint64_t features = 0;
+ int err = 0;
+
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
* we know these will only support creating one kind of guest CPU,
* which is its preferred CPU type. Fortunately these old kernels
@@ -474,8 +497,50 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf)
ahcf->target = init.target;
ahcf->dtb_compatible = "arm,arm-v8";
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
+ ARM64_SYS_REG(3, 0, 0, 6, 0));
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
+ ARM64_SYS_REG(3, 0, 0, 6, 1));
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
+ ARM64_SYS_REG(3, 0, 0, 4, 0));
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
+ ARM64_SYS_REG(3, 0, 0, 4, 1));
+
+ /*
+ * Note that if AArch32 support is not present in the host,
+ * the AArch32 sysregs are present to be read, but will
+ * return UNKNOWN values. This is neither better nor worse
+ * than skipping the reads and leaving 0, as we must avoid
+ * considering the values in every case.
+ */
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
+ ARM64_SYS_REG(3, 0, 0, 2, 0));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
+ ARM64_SYS_REG(3, 0, 0, 2, 1));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
+ ARM64_SYS_REG(3, 0, 0, 2, 2));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
+ ARM64_SYS_REG(3, 0, 0, 2, 3));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
+ ARM64_SYS_REG(3, 0, 0, 2, 4));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
+ ARM64_SYS_REG(3, 0, 0, 2, 5));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
+ ARM64_SYS_REG(3, 0, 0, 2, 7));
+
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
+ ARM64_SYS_REG(3, 0, 0, 3, 0));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
+ ARM64_SYS_REG(3, 0, 0, 3, 1));
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
+ ARM64_SYS_REG(3, 0, 0, 3, 2));
+
kvm_arm_destroy_scratch_host_vcpu(fdarray);
+ if (err < 0) {
+ return false;
+ }
+
/* We can assume any KVM supporting CPU is at least a v8
* with VFPv4+Neon; this in turn implies most of the other
* feature bits.
--
2.17.2
- [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Richard Henderson, 2018/11/02
- [Qemu-arm] [PATCH v2 4/5] target/arm: Fill in ARMISARegisters for kvm32, Richard Henderson, 2018/11/02
- [Qemu-arm] [PATCH v2 2/5] target/arm: Fill in ARMISARegisters for kvm64,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 1/5] target/arm: Install ARMISARegisters from kvm host, Richard Henderson, 2018/11/02
- [Qemu-arm] [PATCH v2 3/5] target/arm: Introduce read_sys_reg32 for kvm32, Richard Henderson, 2018/11/02
- [Qemu-arm] [PATCH v2 5/5] target/arm: Convert t32ee from feature bit to isar3 test, Richard Henderson, 2018/11/02
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Peter Maydell, 2018/11/02
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Christoffer Dall, 2018/11/02
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Richard Henderson, 2018/11/03
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Marc Zyngier, 2018/11/03
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Richard Henderson, 2018/11/04
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Marc Zyngier, 2018/11/04
- Re: [Qemu-arm] [PATCH v2 0/5] target/arm: KVM vs ARMISARegisters, Mark Rutland, 2018/11/05