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[Qemu-arm] [PATCH v4 13/20] intc/arm_gic: Implement virtualization exten
From: |
Luc Michel |
Subject: |
[Qemu-arm] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) |
Date: |
Sat, 14 Jul 2018 19:15:54 +0200 |
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 50cbbfbe24..28ecf0c1fc 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1360,9 +1360,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,
int offset,
case 0xd0: case 0xd4: case 0xd8: case 0xdc:
{
int regno = (offset - 0xd0) / 4;
+ int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
- if (regno >= GIC_NR_APRS || s->revision != 2) {
+ if (regno >= nr_aprs || s->revision != 2) {
*data = 0;
+ } else if (gic_is_vcpu(cpu)) {
+ *data = s->h_apr[gic_get_vcpu_real_id(cpu)];
} else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
*data = gic_apr_ns_view(s, regno, cpu);
@@ -1376,7 +1379,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int
offset,
int regno = (offset - 0xe0) / 4;
if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) ||
- gic_cpu_ns_access(s, cpu, attrs)) {
+ gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) {
*data = 0;
} else {
*data = s->nsapr[regno][cpu];
@@ -1411,7 +1414,8 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu,
int offset,
s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
}
} else {
- s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR);
+ int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
+ s->bpr[cpu] = MAX(value & 0x7, min_bpr);
}
break;
case 0x10: /* End Of Interrupt */
@@ -1428,11 +1432,14 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu,
int offset,
case 0xd0: case 0xd4: case 0xd8: case 0xdc:
{
int regno = (offset - 0xd0) / 4;
+ int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
- if (regno >= GIC_NR_APRS || s->revision != 2) {
+ if (regno >= nr_aprs || s->revision != 2) {
return MEMTX_OK;
}
- if (gic_cpu_ns_access(s, cpu, attrs)) {
+ if (gic_is_vcpu(cpu)) {
+ s->h_apr[gic_get_vcpu_real_id(cpu)] = value;
+ } else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
gic_apr_write_ns_view(s, regno, cpu, value);
} else {
@@ -1447,6 +1454,9 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu,
int offset,
if (regno >= GIC_NR_APRS || s->revision != 2) {
return MEMTX_OK;
}
+ if (gic_is_vcpu(cpu)) {
+ return MEMTX_OK;
+ }
if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
return MEMTX_OK;
}
--
2.18.0
- [Qemu-arm] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers, (continued)
- [Qemu-arm] [PATCH v4 03/20] intc/arm_gic: Remove some dead code and put some functions static, Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio), Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write),
Luc Michel <=
- [Qemu-arm] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions, Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq, Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 01/20] intc/arm_gic: Refactor operations on the distributor, Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function, Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface, Luc Michel, 2018/07/14
- [Qemu-arm] [PATCH v4 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state, Luc Michel, 2018/07/14