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Re: [Qemu-arm] [PATCH v6 00/35] target/arm SVE patches
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [PATCH v6 00/35] target/arm SVE patches |
Date: |
Thu, 28 Jun 2018 15:55:49 +0100 |
User-agent: |
mu4e 1.1.0; emacs 26.1.50 |
Peter Maydell <address@hidden> writes:
> On 28 June 2018 at 12:30, Alex Bennée <address@hidden> wrote:
>>
>> Richard Henderson <address@hidden> writes:
>>
>>> This is the remainder of the SVE enablement patches,
>>> with an extra bonus patch to enable ARMv8.2-DotProd.
>>>
>>> V6 updates based on review.
>>
>> One failure from the VQ3 test set:
>>
>> ../qemu.git/aarch64-linux-user/qemu-aarch64 \
>> ./risu --test-sve=3 \
>> address@hidden/insn_sdiv_z_p_zz___INC.risu.bin \
>> address@hidden/insn_sdiv_z_p_zz___INC.risu.bin.trace
>>
>> Gives:
>>
>> loading test image
>> address@hidden/insn_sdiv_z_p_zz___INC.risu.bin...
>> starting apprentice image at 0x4000801000
>> starting image
>> fish: “../qemu.git/aarch64-linux-user/…” terminated by signal SIGFPE
>> (Floating point exception)
>
> Do you have the insn that it's barfing on? In particular,
> I'm guessing from the test name that this is for something
> covered by one of the SDIV_zpzz lines in sve.decode, which
> is already in master rather than in this test series.
> If that's true, then it shouldn't block applying this set...
#0 0x000055555569297f in helper_sve_sdiv_zpzz_s (vd=0x555557a522e0,
vn=0x555557a522e0, vm=0x555557a51fe0, vg=0x555557a52be0, desc=<optimised out>)
at /home/alex/lsrc/qemu/qemu.git/target/arm/sve_helper.c:480
#1 0x0000555555b1283f in static_code_gen_buffer ()
#2 0x00005555555ea0d8 in cpu_tb_exec (itb=<optimised out>, cpu=0x555557a50320)
at /home/alex/lsrc/qemu/qemu.git/accel/tcg/cpu-exec.c:171
#3 cpu_loop_exec_tb (tb_exit=<synthetic pointer>, last_tb=<synthetic pointer>,
tb=<optimised out>, cpu=0x555557a50320) at
/home/alex/lsrc/qemu/qemu.git/accel/tcg/cpu-exec.c:612
#4 cpu_exec (address@hidden) at
/home/alex/lsrc/qemu/qemu.git/accel/tcg/cpu-exec.c:722
#5 0x000055555560ad40 in cpu_loop (env=0x555557a50320) at
/home/alex/lsrc/qemu/qemu.git/linux-user/aarch64/cpu_loop.c:82
#6 0x00005555555afb0c in main (argc=<optimised out>, argv=0x7fffffffdea8,
envp=<optimised out>) at /home/alex/lsrc/qemu/qemu.git/linux-user/main.c:813
#0 0x000055555569297f in helper_sve_sdiv_zpzz_s (vd=0x555557a522e0,
vn=0x555557a522e0, vm=0x555557a51fe0, vg=0x555557a52be0, desc=<optimised out>)
at /home/alex/lsrc/qemu/qemu.git/target/arm/sve_helper.c:480
480 DO_ZPZZ(sve_sdiv_zpzz_s, int32_t, H1_4, DO_DIV)
=> 0x55555569297f <helper_sve_sdiv_zpzz_s+63>: idiv %r10d
0x555555692982 <helper_sve_sdiv_zpzz_s+66>: mov %eax,%r11d
0x555555692985 <helper_sve_sdiv_zpzz_s+69>: mov %r11d,(%rdi,%r8,1)
0x555555692989 <helper_sve_sdiv_zpzz_s+73>: add $0x4,%r8
0x55555569298d <helper_sve_sdiv_zpzz_s+77>: shr $0x4,%r9w
A syntax error in expression, near `./ $r10d'.
r10d $6 = 0xffffffff
rax $7 = 0x80000000
rdx $8 = 0xffffffff
Yeah so from something already merged in.
--
Alex Bennée
- Re: [Qemu-arm] [PATCH v6 31/35] target/arm: Implement SVE fp complex multiply add (indexed), (continued)
- [Qemu-arm] [PATCH v6 33/35] target/arm: Implement SVE dot product (indexed), Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 34/35] target/arm: Enable SVE for aarch64-linux-user, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 35/35] target/arm: Implement ARMv8.2-DotProd, Richard Henderson, 2018/06/27
- Re: [Qemu-arm] [PATCH v6 00/35] target/arm SVE patches, Alex Bennée, 2018/06/28
- Re: [Qemu-arm] [PATCH v6 00/35] target/arm SVE patches, Alex Bennée, 2018/06/28