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[Qemu-arm] [PATCH v6 22/35] target/arm: Implement SVE floating-point tri
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v6 22/35] target/arm: Implement SVE floating-point trig multiply-add coefficient |
Date: |
Tue, 26 Jun 2018 21:33:15 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper-sve.h | 4 +++
target/arm/sve_helper.c | 70 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 27 +++++++++++++++
target/arm/sve.decode | 3 ++
4 files changed, 104 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 44a98440c9..aca137fc37 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -1037,6 +1037,10 @@ DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
void, env, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 0486cb1e5e..79358c804b 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3428,6 +3428,76 @@ DO_FPCMP_PPZ0_ALL(sve_fcmlt0, DO_FCMLT)
DO_FPCMP_PPZ0_ALL(sve_fcmeq0, DO_FCMEQ)
DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)
+/* FP Trig Multiply-Add. */
+
+void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
+{
+ static const float16 coeff[16] = {
+ 0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x3c00, 0xb800, 0x293a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ };
+ intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float16);
+ intptr_t x = simd_data(desc);
+ float16 *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i++) {
+ float16 mm = m[i];
+ intptr_t xx = x;
+ if (float16_is_neg(mm)) {
+ mm = float16_abs(mm);
+ xx += 8;
+ }
+ d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs);
+ }
+}
+
+void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
+{
+ static const float32 coeff[16] = {
+ 0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9,
+ 0x36369d6d, 0x00000000, 0x00000000, 0x00000000,
+ 0x3f800000, 0xbf000000, 0x3d2aaaa6, 0xbab60705,
+ 0x37cd37cc, 0x00000000, 0x00000000, 0x00000000,
+ };
+ intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float32);
+ intptr_t x = simd_data(desc);
+ float32 *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i++) {
+ float32 mm = m[i];
+ intptr_t xx = x;
+ if (float32_is_neg(mm)) {
+ mm = float32_abs(mm);
+ xx += 8;
+ }
+ d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs);
+ }
+}
+
+void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
+{
+ static const float64 coeff[16] = {
+ 0x3ff0000000000000ull, 0xbfc5555555555543ull,
+ 0x3f8111111110f30cull, 0xbf2a01a019b92fc6ull,
+ 0x3ec71de351f3d22bull, 0xbe5ae5e2b60f7b91ull,
+ 0x3de5d8408868552full, 0x0000000000000000ull,
+ 0x3ff0000000000000ull, 0xbfe0000000000000ull,
+ 0x3fa5555555555536ull, 0xbf56c16c16c13a0bull,
+ 0x3efa01a019b1e8d8ull, 0xbe927e4f7282f468ull,
+ 0x3e21ee96d2641b13ull, 0xbda8f76380fbb401ull,
+ };
+ intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float64);
+ intptr_t x = simd_data(desc);
+ float64 *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i++) {
+ float64 mm = m[i];
+ intptr_t xx = x;
+ if (float64_is_neg(mm)) {
+ mm = float64_abs(mm);
+ xx += 8;
+ }
+ d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs);
+ }
+}
+
/*
* Load contiguous data, protected by a governing predicate.
*/
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index cfee256be9..a86ebc0a91 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3597,6 +3597,33 @@ DO_PPZ(FCMNE_ppz0, fcmne0)
#undef DO_PPZ
+/*
+ *** SVE floating-point trig multiply-add coefficient
+ */
+
+static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn)
+{
+ static gen_helper_gvec_3_ptr * const fns[3] = {
+ gen_helper_sve_ftmad_h,
+ gen_helper_sve_ftmad_s,
+ gen_helper_sve_ftmad_d,
+ };
+
+ if (a->esz == 0) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ status, vsz, vsz, a->imm, fns[a->esz - 1]);
+ tcg_temp_free_ptr(status);
+ }
+ return true;
+}
+
/*
*** SVE Floating Point Accumulating Reduction Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a774becd6c..fdcc252eaa 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -800,6 +800,9 @@ FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . .....
@rdn_i1
FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
+# SVE floating-point trig multiply-add coefficient
+FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx
+
### SVE FP Multiply-Add Group
# SVE floating-point multiply-accumulate writing addend
--
2.17.1
- [Qemu-arm] [PATCH v6 15/35] target/arm: Implement SVE scatter store vector immediate, (continued)
- [Qemu-arm] [PATCH v6 15/35] target/arm: Implement SVE scatter store vector immediate, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 16/35] target/arm: Implement SVE floating-point compare vectors, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 11/35] target/arm: Implement SVE scatter stores, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 13/35] target/arm: Implement SVE gather loads, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 14/35] target/arm: Implement SVE first-fault gather loads, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 18/35] target/arm: Implement SVE Floating Point Multiply Indexed Group, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 19/35] target/arm: Implement SVE FP Fast Reduction Group, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 17/35] target/arm: Implement SVE floating-point arithmetic with immediate, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 20/35] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 22/35] target/arm: Implement SVE floating-point trig multiply-add coefficient,
Richard Henderson <=
- [Qemu-arm] [PATCH v6 21/35] target/arm: Implement SVE FP Compare with Zero Group, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 24/35] target/arm: Implement SVE floating-point convert to integer, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 25/35] target/arm: Implement SVE floating-point round to integral value, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 26/35] target/arm: Implement SVE floating-point unary operations, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 27/35] target/arm: Implement SVE MOVPRFX, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 23/35] target/arm: Implement SVE floating-point convert precision, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 28/35] target/arm: Implement SVE floating-point complex add, Richard Henderson, 2018/06/27
- [Qemu-arm] [PATCH v6 30/35] target/arm: Pass index to AdvSIMD FCMLA (indexed), Richard Henderson, 2018/06/27