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[Qemu-arm] [PATCH v3-a 19/27] target/arm: Implement SVE Compute Vector A
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v3-a 19/27] target/arm: Implement SVE Compute Vector Address Group |
Date: |
Wed, 16 May 2018 15:29:59 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper-sve.h | 5 +++++
target/arm/sve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 36 ++++++++++++++++++++++++++++++++++
target/arm/sve.decode | 12 ++++++++++++
4 files changed, 93 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 00e3cd48bb..5280d375f9 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -380,6 +380,11 @@ DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_adr_p32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_adr_p64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_adr_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve_adr_u32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index f43640c1eb..7fa8394aec 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1062,3 +1062,43 @@ void HELPER(sve_index_d)(void *vd, uint64_t start,
d[i] = start + i * incr;
}
}
+
+void HELPER(sve_adr_p32)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 4;
+ uint32_t sh = simd_data(desc);
+ uint32_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ d[i] = n[i] + (m[i] << sh);
+ }
+}
+
+void HELPER(sve_adr_p64)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t sh = simd_data(desc);
+ uint64_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ d[i] = n[i] + (m[i] << sh);
+ }
+}
+
+void HELPER(sve_adr_s32)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t sh = simd_data(desc);
+ uint64_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ d[i] = n[i] + ((uint64_t)(int32_t)m[i] << sh);
+ }
+}
+
+void HELPER(sve_adr_u32)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t sh = simd_data(desc);
+ uint64_t *d = vd, *n = vn, *m = vm;
+ for (i = 0; i < opr_sz; i += 1) {
+ d[i] = n[i] + ((uint64_t)(uint32_t)m[i] << sh);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 2c2218bc31..8924848463 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -893,6 +893,42 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a,
uint32_t insn)
return true;
}
+/*
+ *** SVE Compute Vector Address Group
+ */
+
+static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
+{
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, a->imm, fn);
+ }
+ return true;
+}
+
+static bool trans_ADR_p32(DisasContext *s, arg_rrri *a, uint32_t insn)
+{
+ return do_adr(s, a, gen_helper_sve_adr_p32);
+}
+
+static bool trans_ADR_p64(DisasContext *s, arg_rrri *a, uint32_t insn)
+{
+ return do_adr(s, a, gen_helper_sve_adr_p64);
+}
+
+static bool trans_ADR_s32(DisasContext *s, arg_rrri *a, uint32_t insn)
+{
+ return do_adr(s, a, gen_helper_sve_adr_s32);
+}
+
+static bool trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn)
+{
+ return do_adr(s, a, gen_helper_sve_adr_u32);
+}
+
/*
*** SVE Predicate Logical Operations Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index b24f6b2f1b..691876de4e 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -48,6 +48,7 @@
&rr_esz rd rn esz
&rri rd rn imm
+&rrri rd rn rm imm
&rri_esz rd rn imm esz
&rrr_esz rd rn rm esz
&rpr_esz rd pg rn esz
@@ -75,6 +76,9 @@
# Three operand, vector element size
@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
+# Three operand with "memory" size, aka immediate left shift
address@hidden ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
+
# Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx
@@ -276,6 +280,14 @@ ASR_zzw 00000100 .. 1 ..... 1000 00 ..... .....
@rd_rn_rm
LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
+### SVE Compute Vector Address Group
+
+# SVE vector address generation
+ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
+ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
+ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
+ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
+
### SVE Predicate Logical Operations Group
# SVE predicate logical operations
--
2.17.0
- [Qemu-arm] [PATCH v3-a 08/27] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, (continued)
- [Qemu-arm] [PATCH v3-a 08/27] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 12/27] target/arm: Implement SVE bitwise shift by wide elements (predicated), Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 11/27] target/arm: Implement SVE bitwise shift by vector (predicated), Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 10/27] target/arm: Implement SVE bitwise shift by immediate (predicated), Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 15/27] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 14/27] target/arm: Implement SVE Integer Multiply-Add Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 16/27] target/arm: Implement SVE Index Generation Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 13/27] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 17/27] target/arm: Implement SVE Stack Allocation Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 19/27] target/arm: Implement SVE Compute Vector Address Group,
Richard Henderson <=
- [Qemu-arm] [PATCH v3-a 18/27] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 21/27] target/arm: Implement SVE floating-point trig select coefficient, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 20/27] target/arm: Implement SVE floating-point exponential accelerator, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 23/27] target/arm: Implement SVE Bitwise Immediate Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 22/27] target/arm: Implement SVE Element Count Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 25/27] target/arm: Implement SVE Permute - Extract Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 24/27] target/arm: Implement SVE Integer Wide Immediate - Predicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 26/27] target/arm: Extend vec_reg_offset to larger sizes, Richard Henderson, 2018/05/16