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Re: [Qemu-arm] [PATCH 2/2] target/arm: Tidy condition in disas_simd_two_
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [PATCH 2/2] target/arm: Tidy condition in disas_simd_two_reg_misc |
Date: |
Wed, 02 May 2018 10:47:17 +0100 |
User-agent: |
mu4e 1.1.0; emacs 26.1 |
Richard Henderson <address@hidden> writes:
> Path analysis shows that size == 3 && !is_q has been eliminated.
>
> Fixes: Coverity CID1385853
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/arm/translate-a64.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 97950dce1a..6d49f30b4a 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -11473,7 +11473,11 @@ static void disas_simd_two_reg_misc(DisasContext *s,
> uint32_t insn)
> /* All 64-bit element operations can be shared with scalar 2misc */
> int pass;
>
> - for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
> + /* Coverity claims (size == 3 && !is_q) has been eliminated
> + * from all paths leading to here.
> + */
> + tcg_debug_assert(is_q);
> + for (pass = 0; pass < 2; pass++) {
> TCGv_i64 tcg_op = tcg_temp_new_i64();
> TCGv_i64 tcg_res = tcg_temp_new_i64();
--
Alex Bennée