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Re: [Qemu-arm] [PATCH v5 2/3] target/arm: Add "_S" suffix to the secure
From: |
Alex Bennée |
Subject: |
Re: [Qemu-arm] [PATCH v5 2/3] target/arm: Add "_S" suffix to the secure version of a sysreg |
Date: |
Wed, 04 Apr 2018 11:51:20 +0100 |
User-agent: |
mu4e 1.1.0; emacs 26.0.91 |
Abdallah Bouassida <address@hidden> writes:
> This is a preparation for the coming feature of creating dynamically an XML
> description for the ARM sysregs.
> Add "_S" suffix to the secure version of sysregs that have both S and NS views
> Replace (S) and (NS) by _S and _NS for the register that are manually defined,
> so all the registers follow the same convention.
>
> Signed-off-by: Abdallah Bouassida <address@hidden>
> Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/arm/helper.c | 29 ++++++++++++++++++-----------
> 1 file changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index db8c925..1360a14 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -695,12 +695,12 @@ static const ARMCPRegInfo cp_reginfo[] = {
> * the secure register to be properly reset and migrated. There is also
> no
> * v8 EL1 version of the register so the non-secure instance stands
> alone.
> */
> - { .name = "FCSEIDR(NS)",
> + { .name = "FCSEIDR",
> .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
> .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
> .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
> .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
> - { .name = "FCSEIDR(S)",
> + { .name = "FCSEIDR_S",
> .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
> .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
> .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
> @@ -716,7 +716,7 @@ static const ARMCPRegInfo cp_reginfo[] = {
> .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
> .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
> .resetvalue = 0, .writefn = contextidr_write, .raw_writefn =
> raw_write, },
> - { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
> + { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
> .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
> .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
> .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
> @@ -1967,7 +1967,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
> cp15.c14_timer[GTIMER_PHYS].ctl),
> .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
> },
> - { .name = "CNTP_CTL(S)",
> + { .name = "CNTP_CTL_S",
> .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
> .secure = ARM_CP_SECSTATE_S,
> .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
> @@ -2006,7 +2006,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
> .accessfn = gt_ptimer_access,
> .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
> },
> - { .name = "CNTP_TVAL(S)",
> + { .name = "CNTP_TVAL_S",
> .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
> .secure = ARM_CP_SECSTATE_S,
> .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
> @@ -2060,7 +2060,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
> .accessfn = gt_ptimer_access,
> .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
> },
> - { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
> + { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
> .secure = ARM_CP_SECSTATE_S,
> .access = PL1_RW | PL0_R,
> .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
> @@ -5563,7 +5563,8 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error
> **errp)
>
> static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
> void *opaque, int state, int secstate,
> - int crm, int opc1, int opc2)
> + int crm, int opc1, int opc2,
> + const char *name)
> {
> /* Private utility function for define_one_arm_cp_reg_with_opaque():
> * add a single reginfo struct to the hash table.
> @@ -5573,6 +5574,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
> ARMCPRegInfo *r,
> int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
> int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
>
> + r2->name = g_strdup(name);
> /* Reset the secure state to the specific incoming state. This is
> * necessary as the register may have been defined with both states.
> */
> @@ -5804,19 +5806,24 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
> /* Under AArch32 CP registers can be common
> * (same for secure and non-secure world) or banked.
> */
> + char *name;
> +
> switch (r->secure) {
> case ARM_CP_SECSTATE_S:
> case ARM_CP_SECSTATE_NS:
> add_cpreg_to_hashtable(cpu, r, opaque, state,
> - r->secure, crm, opc1,
> opc2);
> + r->secure, crm, opc1,
> opc2,
> + r->name);
> break;
> default:
> + name = g_strdup_printf("%s_S", r->name);
> add_cpreg_to_hashtable(cpu, r, opaque, state,
> ARM_CP_SECSTATE_S,
> - crm, opc1, opc2);
> + crm, opc1, opc2, name);
> + g_free(name);
> add_cpreg_to_hashtable(cpu, r, opaque, state,
> ARM_CP_SECSTATE_NS,
> - crm, opc1, opc2);
> + crm, opc1, opc2, r->name);
> break;
> }
> } else {
> @@ -5824,7 +5831,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
> * of AArch32 */
> add_cpreg_to_hashtable(cpu, r, opaque, state,
> ARM_CP_SECSTATE_NS,
> - crm, opc1, opc2);
> + crm, opc1, opc2, r->name);
> }
> }
> }
--
Alex Bennée
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