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[Qemu-arm] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01]
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01] |
Date: |
Fri, 16 Mar 2018 16:30:59 -0400 |
A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01].
pmceid[01] are already being initialized to zero for both A15 and A57.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 991d764..8c4db31 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -201,6 +201,8 @@ static void aarch64_a53_initfn(Object *obj)
cpu->id_isar5 = 0x00011121;
cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
+ cpu->pmceid0 = 0x00000000;
+ cpu->pmceid1 = 0x00000000;
cpu->id_aa64isar0 = 0x00011120;
cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
cpu->dbgdidr = 0x3516d000;
--
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[Qemu-arm] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/03/16