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[Qemu-arm] [PATCH v2 24/67] target/arm: Implement SVE Bitwise Immediate
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 24/67] target/arm: Implement SVE Bitwise Immediate Group |
Date: |
Sat, 17 Feb 2018 10:22:40 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
target/arm/sve.decode | 17 ++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 702f20e97b..21b1e4df85 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -34,6 +34,8 @@
#include "translate-a64.h"
typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t,
+ int64_t, uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
@@ -1648,6 +1650,54 @@ static void trans_SINCDEC_v(DisasContext *s,
arg_incdec2_cnt *a,
}
}
+/*
+ *** SVE Bitwise Immediate Group
+ */
+
+static void do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
+{
+ unsigned vsz;
+ uint64_t imm;
+
+ if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
+ extract32(a->dbm, 0, 6),
+ extract32(a->dbm, 6, 6))) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ vsz = vec_full_reg_size(s);
+ gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn), imm, vsz, vsz);
+}
+
+static void trans_AND_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
+{
+ do_zz_dbm(s, a, tcg_gen_gvec_andi);
+}
+
+static void trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
+{
+ do_zz_dbm(s, a, tcg_gen_gvec_ori);
+}
+
+static void trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a, uint32_t insn)
+{
+ do_zz_dbm(s, a, tcg_gen_gvec_xori);
+}
+
+static void trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn)
+{
+ uint64_t imm;
+ if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1),
+ extract32(a->dbm, 0, 6),
+ extract32(a->dbm, 6, 6))) {
+ unallocated_encoding(s);
+ return;
+ }
+ do_dupi_z(s, a->rd, imm);
+}
+
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 5690b5fcb9..0990d135f4 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -50,6 +50,7 @@
&rr_esz rd rn esz
&rri rd rn imm
+&rr_dbm rd rn dbm
&rrri rd rn rm imm
&rri_esz rd rn imm esz
&rrr_esz rd rn rm esz
@@ -112,6 +113,10 @@
@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
&rri_esz esz=%tszimm16_esz
+# Two register operand, one encoded bitmask.
address@hidden ........ .. .... dbm:13 rd:5 \
+ &rr_dbm rn=%reg_movprfx
+
# Basic Load/Store with 9-bit immediate offset
@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
&rri imm=%imm9_16_10
@@ -331,6 +336,18 @@ INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... .....
@incdec2_cnt u=1
# Note these require esz != 0.
SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
+### SVE Bitwise Immediate Group
+
+# SVE bitwise logical with immediate (unpredicated)
+ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
+EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
+AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
+
+# SVE broadcast bitmask immediate
+DUPM 00000101 11 0000 dbm:13 rd:5
+
+### SVE Predicate Logical Operations Group
+
# SVE predicate logical operations
AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
--
2.14.3
- Re: [Qemu-arm] [PATCH v2 21/67] target/arm: Implement SVE floating-point exponential accelerator, (continued)
- [Qemu-arm] [PATCH v2 20/67] target/arm: Implement SVE Compute Vector Address Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 18/67] target/arm: Implement SVE Stack Allocation Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 19/67] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 22/67] target/arm: Implement SVE floating-point trig select coefficient, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 24/67] target/arm: Implement SVE Bitwise Immediate Group,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 23/67] target/arm: Implement SVE Element Count Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 26/67] target/arm: Implement SVE Permute - Extract Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 25/67] target/arm: Implement SVE Integer Wide Immediate - Predicated Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 28/67] target/arm: Implement SVE Permute - Predicates Group, Richard Henderson, 2018/02/17