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[Qemu-arm] [PATCH v2 05/20] sdhci: refactor common sysbus/pci realize()
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-arm] [PATCH v2 05/20] sdhci: refactor common sysbus/pci realize() into sdhci_realizefn() |
Date: |
Fri, 15 Dec 2017 00:15:32 -0300 |
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
hw/sd/sdhci.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index dbdfd54350..fc5bac5cb9 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1191,6 +1191,15 @@ static void sdhci_initfn(SDHCIState *s)
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer,
s);
}
+static void sdhci_realizefn(SDHCIState *s, Error **errp)
+{
+ s->buf_maxsz = sdhci_get_fifolen(s);
+ s->fifo_buffer = g_malloc0(s->buf_maxsz);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
+ SDHC_REGISTERS_MAP_SIZE);
+}
+
static void sdhci_uninitfn(SDHCIState *s)
{
timer_del(s->insert_timer);
@@ -1281,12 +1290,11 @@ static void sdhci_pci_realize(PCIDevice *dev, Error
**errp)
SDHCIState *s = PCI_SDHCI(dev);
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
+
sdhci_initfn(s);
- s->buf_maxsz = sdhci_get_fifolen(s);
- s->fifo_buffer = g_malloc0(s->buf_maxsz);
+ sdhci_realizefn(s, errp);
+
s->irq = pci_allocate_irq(dev);
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
- SDHC_REGISTERS_MAP_SIZE);
pci_register_bar(dev, 0, 0, &s->iomem);
}
@@ -1343,11 +1351,9 @@ static void sdhci_sysbus_realize(DeviceState *dev, Error
** errp)
SDHCIState *s = SYSBUS_SDHCI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- s->buf_maxsz = sdhci_get_fifolen(s);
- s->fifo_buffer = g_malloc0(s->buf_maxsz);
+ sdhci_realizefn(s, errp);
+
sysbus_init_irq(sbd, &s->irq);
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
- SDHC_REGISTERS_MAP_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
}
--
2.15.1
- [Qemu-arm] [PATCH v2 00/20] SDHCI: housekeeping, add a qtest and fix few issues, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 01/20] sdhci: clean up includes, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 02/20] sdhci: use deposit64(), Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 03/20] sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h", Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 04/20] sdhci: refactor same sysbus/pci properties into a common one, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 05/20] sdhci: refactor common sysbus/pci realize() into sdhci_realizefn(),
Philippe Mathieu-Daudé <=
- [Qemu-arm] [PATCH v2 06/20] sdhci: refactor common sysbus/pci class_init() into sdhci_class_init(), Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 07/20] sdhci: refactor common sysbus/pci unrealize() into sdhci_unrealizefn(), Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 08/20] sdhci: use qemu_log_mask(UNIMP) instead of fprintf(), Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 09/20] sdhci: convert the DPRINT() calls into trace events, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 10/20] sdhci: add a GPIO for the access control LED, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 11/20] sdhci: add a "dma-memory" property, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 13/20] sdhci: Implement write method of ACMD12ERRSTS register, Philippe Mathieu-Daudé, 2017/12/14
- [Qemu-arm] [PATCH v2 12/20] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only, Philippe Mathieu-Daudé, 2017/12/14