Re: [Qemu-arm] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero)

[Richard Henderson]

On 10/13/2017 09:24 AM, Alex Bennée wrote:
> @@ -7792,7 +7793,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int 
> opcode,
>              swap = true;
>              /* fall through */
>          case 0x2c: /* FCMGT (zero) */
> -            genfn = gen_helper_neon_cgt_f32;
> +            genfn = hp ? gen_helper_advsimd_cgt_f16 : 
> gen_helper_neon_cgt_f32;
>              break;
>          case 0x2d: /* FCMEQ (zero) */
>              genfn = gen_helper_neon_ceq_f32;
> @@ -7814,7 +7815,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int 
> opcode,
>          }
>  
>          for (pass = 0; pass < maxpasses; pass++) {
> -            read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
> +            read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32);
>              if (swap) {
>                  genfn(tcg_res, tcg_zero, tcg_op, fpst);
>              } else {

I don't see a change to maxpasses here.


>          case 0x2: /* FADD */
>              gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
>              break;
> +        case 0x6: /* FMAX */
> +            gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
> +            break;
>          case 0x23: /* FMUL */
>              gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
>              break;

Belongs in another patch?


r~