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Re: [Qemu-arm] [PATCH v11 3/5] msf2: Add Smartfusion2 SPI controller
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v11 3/5] msf2: Add Smartfusion2 SPI controller |
Date: |
Tue, 10 Oct 2017 13:54:03 +0100 |
On 20 September 2017 at 21:17, Philippe Mathieu-Daudé <address@hidden> wrote:
> From: Subbaraya Sundeep <address@hidden>
>
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
> Tested-by: Philippe Mathieu-Daudé <address@hidden>
> +#define FRAMESZ_MASK 0x1F
> +static void set_fifodepth(MSSSpiState *s)
> +{
> + unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> +
> + if (size <= 8) {
> + s->fifo_depth = 32;
> + } else if (size <= 16) {
> + s->fifo_depth = 16;
> + } else if (size <= 32) {
> + s->fifo_depth = 8;
> + } else {
> + s->fifo_depth = 4;
> + }
> +}
Hi. Coverity points out (CID 1381483) that the "else" case here
is dead code, because the FRAMESZ_MASK of 0x1F means that size
cannot be 32 or more.
Paolo kindly checked up with the spec at
https://www.eecs.umich.edu/courses/eecs373/readings/Actel_SmartFusion_MSS_UserGuide.pdf
which says that this register's field is bits [5:0] which
would imply an 0x3f mask is needed. On the other hand it also
says that "maximum value is 32", so what is the else clause
doing anyway?
thanks
-- PMM
- Re: [Qemu-arm] [PATCH v11 3/5] msf2: Add Smartfusion2 SPI controller,
Peter Maydell <=