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[Qemu-arm] [RFC PATCH for 2.11 06/23] softfloat3c: silence compiler warn
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [RFC PATCH for 2.11 06/23] softfloat3c: silence compiler warning |
Date: |
Thu, 20 Jul 2017 16:04:09 +0100 |
While you could pass a 0 size_words to the function it would be a bug.
At least by ensuring the leg is followed it stops the compiler
complaining about a potential uninitialised access.
Signed-off-by: Alex Bennée <address@hidden>
---
fpu/softfloat3c/s_shiftRightJamM.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fpu/softfloat3c/s_shiftRightJamM.c
b/fpu/softfloat3c/s_shiftRightJamM.c
index 47ba5ddaf9..035d5d3c1f 100644
--- a/fpu/softfloat3c/s_shiftRightJamM.c
+++ b/fpu/softfloat3c/s_shiftRightJamM.c
@@ -66,7 +66,7 @@ void
} while ( i );
ptr = zPtr;
}
- if ( wordDist < size_words ) {
+ if ( wordDist <= size_words ) {
aPtr += indexMultiwordHiBut( size_words, wordDist );
innerDist = dist & 31;
if ( innerDist ) {
--
2.13.0
- [Qemu-arm] [RFC PATCH for 2.11 00/23] Implementing FP16 for ARMv8.2 using SoftFloat2a and 3c, Alex Bennée, 2017/07/20
- [Qemu-arm] [RFC PATCH for 2.11 08/23] target-aarch64: enable SoftFloat3 build for FP16, Alex Bennée, 2017/07/20
- [Qemu-arm] [RFC PATCH for 2.11 09/23] arm: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2017/07/20
- [Qemu-arm] [RFC PATCH for 2.11 11/23] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/07/20
- [Qemu-arm] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same, Alex Bennée, 2017/07/20