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From: | Abdallah Bouassida |
Subject: | [Qemu-arm] [Qemu-devel] [PATCH] target-arm: Bug fix in filling the cp_regs hashtable |
Date: | Fri, 16 Jun 2017 15:42:34 +0100 |
User-agent: | Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 |
Check if the CPU supports AARCH64 before adding the 64bit view of the coprocessor's register to the cp_regs hashtable. Signed-off-by: Abdallah Bouassida <address@hidden> --- Bug description: if a register has the .state = ARM_CP_STATE_BOTH, its 64bit view will be added to the hashtable even if the CPU is not 64bit. target/arm/helper.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2594faa..7fa2889 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5607,11 +5607,13 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, break; } } else { - /* AArch64 registers get mapped to non-secure instance - * of AArch32 */ - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2); + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + /* AArch64 registers get mapped to non-secure instance + * of AArch32 */ + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2); + } } } } -- 1.9.1 |
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