Re: [Qemu-arm] [PATCH 1/3] hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1

[Philippe Mathieu-Daudé]

On 04/26/2017 02:13 PM, Peter Maydell wrote:
> We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr()
> on reset, but this is not correct. The field should reset to
> the minimum value of ICV_BPR0_EL1 plus one.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/intc/arm_gicv3_cpuif.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index 0b20856..d31eba0 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -2014,7 +2014,7 @@ static void icc_reset(CPUARMState *env, const 
> ARMCPRegInfo *ri)
>      cs->ich_hcr_el2 = 0;
>      memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2));
>      cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN |
> -        (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR1_SHIFT) |
> +        ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) |

Indeed "a BPR of 0 is impossible (the minimum value is 1)"

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>

>          (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT);
>  }