Re: [Qemu-arm] [PATCH 3/8] target/arm: optimize rev16() using extract op

[Philippe Mathieu-Daudé]

Hi,

I'll resend as v3, just to confirm this patch is OK:

$ docker run -it -v `pwd`:`pwd` -w `pwd` petersenna/coccinelle --sp-file 
scripts/coccinelle/tcg_gen_extract.cocci --macro-file 
scripts/cocci-macro-file.h target/arm/translate-a64.c
init_defs_builtins: /usr/lib64/coccinelle/standard.h
init_defs: scripts/cocci-macro-file.h
HANDLING: target/arm/translate-a64.c
candidate at target/arm/translate-a64.c:4041
  op_size: i64/i64 (same)
  low_bits: 16 (value: 0xffff)
  len: 0xffff
  len_bits == low_bits
  candidate IS optimizable

candidate at target/arm/translate-a64.c:4047
  op_size: i64/i64 (same)
  low_bits: 16 (value: 0xffff)
  len: 0xffff
  len_bits == low_bits
  candidate IS optimizable

On 05/10/2017 05:05 PM, Philippe Mathieu-Daudé wrote:
> Applied using Coccinelle script.
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
> ---
>  target/arm/translate-a64.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 24de30d92c..7ea130107e 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -4038,14 +4038,12 @@ static void handle_rev16(DisasContext *s, unsigned int 
> sf,
>      tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
>      tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
>
> -    tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
> -    tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
> +    tcg_gen_extract_i64(tcg_tmp, tcg_rn, 16, 0xffff);
>      tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
>      tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
>
>      if (sf) {
> -        tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
> -        tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
> +        tcg_gen_extract_i64(tcg_tmp, tcg_rn, 32, 0xffff);
>          tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
>          tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);